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US 4,657,628 AGranted
Process for patterning local interconnects
AssigneeTexas Instruments Incorporated
InventorsThomas C. Holloway, Thomas E. Tang, Che-Chia Wei, Roger A. Haken, David A. Bell
Life of this patent
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Abstract
A local interconnect system for VLSI integrated circuits. After titanium is deposited for self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a hardmask is deposited and patterned over the titanium. When a conductive titanium nitride layer is formed overall, it will already be patterned according to this hardmask.
Claims11
A process for fabricating integrated circuits including local interconnect, comprising the steps of:
- (a) providing a partially fabricated integrated circuit structure including moat regions, said moat regions incorporating active devices therein;
- (b) depositing a thin layer of metal consisting predominantly of titanium overall;
- (c) depositing a relatively inert material over said titanium in locations defining local interconnect pathways and/or locations of contacts to moat;
- (d) reacting said partially fabricated structure in an atmosphere containing a high portion of nitrogen, whereby portions of said titanium metal over moat regions are predominantly converted to titanium silicide, and portions of said titanium metal over oxide regions are converted predominantly to titanium nitride;
- (e) etching away exposed portions of said titanium and of said titanium nitride, to define local interconnects in predetermined local interconnect locations.
2 more elements
Dependencies are inferred from the claim text.