System for automatic testing of circuits and systems

A system for selectively generating analog and parametric digital signals for application to a unit under test having a plurality of pins, said system including a plurality of test channels, each of said test channels being adapted to be coupled to apply the respective selectively generated analog or parametric digital signal to a different single pin of said unit, each said test channel comprising:

• a memory for storing respective 16-bit digital word equivalents of respective analog and parametric digital signals;
• a splitter coupled to said memory to receive and divide 16-bit digital word equivalents read from said memory into two 8-bit digital words;
• at least one digital to analog converter coupled to said splitter for converting respective 8-bit digital words to respective analog and parametric digital signals;
• means for timing said memory to read said 16-bit digital word equivalents therefrom and for timing said digital to analog converter to convert said 8-bit digital words into said analog and parametric digital signals;
• and means for applying the respective selectively generated analog and parametric digital signals to a said different pin of said unit.

A system for selectively measuring analog and parametric digital output signals of a unit under test having a plurality of pins, said system including a plurality of test channels, each of said test channels being adapted to be coupled to receive said analog and parametric digital signals from a different single pin of said unit, each said test channel comprising:

• a receiver adapted to be coupled to a said different pin of said unit for receiving analog and parametric digital output signals;
• an analog to digital converter coupled to said receiver for converting respective analog and parametric digital output signals to respective 8-bit digital word equivalents;
• combining means coupled to said analog to digital converter for concatenating two respective 8-bit digital words from said analog to digital converter to form respective 16-bit digital words;
• a memory coupled to said combining means for receiving and storing 16-bit digital words formed by said combining means, and means for timing said analog to digital converter to convert said analog and parmaetric digital signals to said 8-bit digital words and for timing said memory to store said 16-bit digital words.

A system for generating functional digital signals for application to a unit under test having a plurality of pins, said unit having a pin capable of functioning as an input pin or a bidirectional pin, said system including at least one test channel adapted to be coupled exclusively to said pin comprising:

• a memory for storing digital words containing information relating to the function of said pin and relating to functional digital signals;
• buffer means coupled to said memory for receiving digital words read from said memory;
• means coupled to said buffer means for receiving a digital word therefrom and for generating one or more digital vectors from said digital word, at least one of said vectors including information as to the function of said pin and at least one of said vectors including a functional digital signal;
• a driver for applying said functional digital signal to said pin;
• and means for enabling said driver in response to a vector which indicates that said pin is an input pin or in response to a vector which indicates that said pin is a bidirectional pin and a vector including a functional digital signal.

A system for generating functional digital signals for application to a unit under test having a plurality of pins, said unit having a pin capable of functioning as an input pin or a bidirectional pin, said system including at least one test channel adapted to be coupled exclusively to said pin comprising:

• a memory for storing digital words in compacted form containing information relating to the function of said pin and relating to functional digital signals;
• a decompaction module for receiving said digital words in compacted form read from said local memory and converting the same to decompacted words;
• register means coupled to said decompaction module for receiving said decompacted words therefrom and for generating one or more digital vectors from said decompacted words, at least one of said vectors including information as to the function of said pin and at least one of said vectors including a functional digital signal;
• a driver for applying functional digital signals from said register means to said pin;
• and means for enabling said driver in response to a vector which indicates either that said pin is an input pin or in response to a vector which indicates that said pin is a bidirectional pin and a vector including a functional digital signal.

A system for selectively generating analog and parametric digital signals for application to a unit under test having a plurality of pins, and for selectively measuring analog and parametric digital output signals of said unit under test, said system including at least one test channel adapted to be coupled to a single pin of said unit functioning as an input pin for selectively applying analog and parametric digital signals thereto and to a single pin of said unit functioning as an output pin for receiving analog and parametric digital signals therefrom, said at least one test channel comprising:

• a memory for storing 16-bit digital word equivalents of analog and parametric digital signals;
• a splitter coupled to said memory to receive and divide respective 16-bit digital word equivalents read from said memory into respective two 8-bit digital words;
• at least one digital to analog converter coupled to said splitter for converting respective 8-bit digital words received from said digital to analog converter to respective analog and parametric digital signals;
• means for applying respective analog and parametric digital signals to said single pin functioning as an input pin;
• a receiver adapted to be coupled to said single pin functioning as an output pin to receive said analog and parametric digital output signals;
• an analog to digital converter coupled to said receiver for converting respective analog and parametric digital output signals received from said receiver to respective 8-bit digital word equivalents;
• combining means coupled to said analog to digital converter for concatenating two respective 8-bit digital words from said analog to digital converter to form a respective 16-bit digital words;
• said memory being coupled to said combining means for receiving and storing said 16-bit digital words, and means for timing said memory to read 16-bit words therefrom, for timing said digital to analog converter to convert 8-bit digital words to analog and parametric digital signals and for timing said analog to digital converter to convert analog and parametric digital signals to 8-bit digital word equivalents.

A system for generating functional digital signals for application to a unit under test having a plurality of pins and for measuring functional digital output signals at the output of said unit, said unit having a pin capable of functioning as an input pin, an output pin or a bidirectional pin, said system including at least one test channel adapted to be coupled exclusively to said pin, each of said test channels comprising:

• a memory for storing digital words;
• buffer means coupled to said memory for receiving respective digital words read from said memory;
• means coupled to said buffer means for receiving said respective digital words therefrom and for generating one or more digital vectors from said digital words, at least one of said words including at least one vector including information as to the function of said pin and at least one vector including a functional digital signal, and at least one of said words including at least one vector including information as to the function of said pin and at least one vector including predetermined logic levels;
• a driver for applying functional digital signals generated by said generating means to said at least one pin;
• means for enabling said driver in response to a vector which indicates that said pin is an input pin, or in response to a vector which indicates that said pin is a bidirectional pin and a vector including a functional digital signal, a receiver adapted to be coupled to said pin for receiving said functional digital output signals;
• means for enabling said receiver in response to a vector which indicates that said pin is an output pin or in response to a vector which indicates that said pin is a bidirectional pin and a vector including predetermined logic levels;
• and logical comparison means coupled to said receiver for comparing respective functional digital signals output by said receiving means to respective predetermined logic levels.