Self-aligned recessed gate process

A gallium arsenide (GaAs) integrated circuit gate structure, comprising:

• a GaAs substrate having a reference surface;
• a first region within the substrate doped to a first dopant concentration and a first depth;
• a second region, adjoining the first region within the substrate, doped to a second dopant concentration greater than the first concentration and defining a dopant gradient boundary extending depthwise into the substrate from the reference surface;
• a dielectric layer covering a portion of the substrate surface including the second doped region and having an edge aligned with said dopant gradient boundary;
• means defining a channel aligned with said edge and recessed depthwise into the substrate in the first doped region to a second depth less than the first depth;
• and
• conductive gate material filling the channel;
• the channel having a sidewall aligned at the reference surface with the edge of the dielectric layer and with the dopant gradient boundary.

A self-aligned gate process for making integrated circuits, comprising

• providing a semi-insulating substrate having a reference surface;
• doping a first defined area of the substrate to a first dopant concentration and a first depth;
• doping a pair of second defined areas of the substrate overlapping the first defined area and spaced apart therein at a first spacing, to a second concentration and a second depth that are greater than the concentration and depth of doping in the first area;
• doping a pair of third defined areas of the substrate, overlapping the second areas within the first area and spaced apart therein to define inward boundaries at a second spacing less than the first spacing, to a third concentration intermediate the first and second concentration and a depth intermediate the first and second depth;
• depositing a dielectric layer atop the substrate, solely over the third areas so as to define two dielectric patches having a gap between them which is aligned with said inward boundaries;
• masking the substrate with a mask layer and forming an opening in the mask layer encompassing at least a portion of said gap;
• and
• depositing a conductive gate material through the opening to form a gate contact within the gap.

A self-aligned gate process for making integrated circuits, comprising:

• providing a semi-insulating substrate having a reference surface;
• depositing a first dielectric layer over said surface;
• applying a layer of photoresist over the first dielectric layer and forming a pair of closely spaced apart openings extending through the photoresist to expose a surface portion of the first dielectric layer through said openings;
• implanting ions through the photoresist openings into the substrate to define two implanted regions having implant boundaries substantially aligned with said openings and spaced apart to define a gap between the regions;
• depositing a second dielectric layer on the photoresist and within the openings atop the surface portion of the first dielectric layer exposed therein;
• removing the layer of photoresist, thereby removing the second dielectric layer deposited thereon and leaving a pair of areas of the second dielectric layer atop the first dielectric layer extending over the pair of implanted regions and having dielectric boundaries spaced closely apart in alignment with said implant boundaries to define a gap in accordance with the spacing of the openings;
• and
• etching within said gap with a first predetermined etchant selectively to remove the first dielectric layer and thereby expose a portion of the substrate bounded by the boundaries of said second dielectric layer;
• and
• depositing a conductive gate material within the gap and the recess to form a gate contact;
• the second dielectric layer being composed of a material which is non-etchable by the first etchant so that the gate contact is aligned with the implant boundaries in accordance with the closely-spaced-apart openings in the photoresist.