Frequency doubler circuit and method

An integrated circuit having at least three inputs to which are applied at least three input pulses in sequence, each pulse having a predetermined phase relationship with respect to each other pulse, the circuit providing a pair of output pulses at an output for each applied pulse, comprising:

• first, second and third pulse doubling circuits each having an input coupled to a respective input of the circuit for producing a pair of pulses for each applied pulse;
• means for sequentially Or'ing said pulses from said pulse doubling circuits at a first circuit node;
• and
• means for increasing the pulsewidths of said pulses appearing at said first circuit node, said means for increasing the pulsewidths including a transistor having its base coupled to said first circuit node, its collector coupled to a first terminal at which is supplied ground potential and its emitter coupled to a second terminal, a capacitor coupled to said second terminal, said capacitor being discharged and then charged as said transistor is rendered conductive and then non-conductive in response to said pulses appearing at said first circuit node and inverter means coupled between said emitter and the output of the circuit for providing an output pulse for each pulse applied to said means for increasing the pulsewidths of said pulses, said pulsewidth of said output pulses being greater than that of said applied pulses.