Programmable semiconductor structures and methods for using the same

A solid state semiconductor cell structure having at least two terminal planes and a plurality of layers of semiconductor material to provide a plurality of interacting semiconductor functions, said cell structure being programmable in a first condition in which the electrical impedance between said two planes is relatively high in both directions, a second condition in which the electrical impedance between said two planes is relatively high in one direction and relatively low in the opposite direction, a third condition in which the electrical impedance between said two planes is relatively high in said opposite direction and relatively low in said one direction, and a fourth condition in which the electrical impedance between said two planes is relatively low in both said directions, and

• addressing means for programming said cell structure at unique selected locations thereof into any one of said conditions.

A programmable cell structure comprising a first plurality of vertically arrayed layers of semiconductor materials arranged to form at least a first pair of series connected vertically disposed back-to-back diodes.

An integrated circuit comprising:

• a multilayered structure of deposited layers of various materials including semiconductor alloy materials, said layers of semiconductor alloy materials being initially deposited as continuous layers, said layers being arranged to provide programmable semiconductor interactions between at least some of said layers so as to perform selected electrical functions at unique selected locations, and to provide said programmable semiconductor interactions in two separate subsets, each separately programmable from the other;
• and
• addressing means for defining said unique selected locations and for enabling the programming of said semiconductor interactions of said semiconductor alloy material layers at said unique selected locations.

A programmable logic array comprising a multilayered structure of a plurality of vertically arrayed layers of various materials including deposited semiconductor alloy materials, said layers of semiconductor materials being initially deposited as continuous layers and at least some of said layers of various materials being arranged to provide semiconductor interactions between said layers for providing individually programmable selected logic functions across said structure at selected locations thereof;

• and
• means defining said selected locations and for enabling the programming of said selected logic functions at said selected locations.

A programmable logic array comprising a multilayered structure of a plurality of vertically arrayed layers of semiconductor materials to form a pair of series connected vertically disposed back-to-back diodes;

• and means for dividing said pair of series connected vertically disposed back-to-back diodes into plural pairs of series connected vertically disposed back-to-back diodes and for enabling the short circuiting of selected ones of said diodes for programming groups of said diode pairs to provide selected logic functions.

A solid state semiconductor programmable switch comprising a plurality of layers of semiconductor material to form at least two series connected vertically disposed cell portions;

• said cell portions being individually programmable for permitting the conduction of current through said switch in only a first direction, or for permitting the conduction of current through said switch in only a second direction opposite said first direction, or for permitting the conduction of current through said switch in both said first and second directions;
• or for preventing the conduction of current through said switch in either said first or second directions.

A method of programming a solid state semiconductor device having a plurality of semiconductor functions in series between a first and a second terminal, said semiconductor functions including a first subset which provides a relatively high impedance in a first direction along said series and a relatively low impedance in a second, opposite, direction along said series, and a second subset which provides a relatively high impedance in said second direction and a relatively low impedance in said first direction, said method comprising forming said device by depositing a plurality of layers of semiconductor material to provide said plurality of semiconductor functions, and selectively programming at least one semiconductor function of said first subset by applying a programming voltage across at least a portion of said device in said first direction.