# US 4,645,951 A · Semiconductor integrated circuit having a C-MOS internal logic block and an output buffer for providing ECL level signals

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 4,645,951 A
- Document ID: US4645951A
- Status: Granted
- Kind: A
- Application number: 06/646,110
- Filed: 1984-08-31
- Granted: 1987-02-24
- Earliest claimed: 1983-08-31
- Assignees: Hitachi, Ltd.
- Inventors: Akira Uragami
- Web page: https://patentgrep.com/patent/US4645951A

## CPC

- H03K 19/01812: {with at least one differential stage}
- H03K 19/017527: {with at least one differential stage}
- H03K 19/09448: {in combination with bipolar transistors [BIMOS]}
- H10W 72/90: Bond pads, in general
- H10D 84/998: {Input and output buffer/driver structures}
- H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor integrated circuit is provided which combines an MOS internal logic circuit (C-MOS in the preferred embodiment) with input and output buffers which have pin-compatibility with ECL circuitry. An ECL-CMOS level-conversion input buffer circuit arranged for a C-MOS internal logic circuit has a pair of emitter-coupled transistors which are responsive to an input signal at an ECL level. Thus, the input buffer circuit operates at a high speed. A CMOS-ECL level-conversion output buffer circuit arranged for the C-MOS internal logic circuit has an amplifying transistor, which has its base responsive to the output signal of the C-MOS internal logic circuit, and an emitter-follower transistor which has its base responsive to the collector signal of said amplifying transistor for generating an output signal at an ECL level at its emitter. Thus, the output buffer circuit operates at a high speed. Utilizing such an arrangement, the circuit can obtain the benefits of lower power consumption for the C-MOS internal logic circuit together with high speed in the buffer stages and ECL compatibility.

## Claims

### Claim 1

A semiconductor integrated circuit comprising:
(1) an internal logic block including a plurality of C-MOS elements;
(2) an input terminal;
(3) an output buffer circuit connected between said internal logic circuit and said output terminal;
(4) a first power source terminal receptive of a ground potential as a first power source voltage; and
(5) a second power source terminal receptive of a negative voltage as a second power source voltage,
wherein said internal logic circuit and said output buffer circuit are operative with said negative voltage, wherein said output buffer circuit has an input terminal receptive of an output signal of said internal logic circuit, wherein said output buffer circuit includes means for generating an output signal at an ECL level at said output terminal in response to receiving the output signal of said internal logic circuit, wherein said means of said output buffer circuit includes an emitter-follower transistor having its emitter connected with said output terminal and its base responsive to the output signal of said internal logic circuit as well as a semiconductor amplifying element having its input electrode responsive to the output signal of said internal logic circuit and its output electrode connected through a load resistor with said ground potential so that the base of said emitter-follower transistor is driven by the signal of said output electrode of said semiconductor amplifying element, wherein said means of said output buffer circuit further comprises a second emitter-follower transistor having its emitter coupled with a second output terminal and its base coupled with a second semiconductor amplifying element, wherein said second semiconductor amplifying element is differentially coupled with said first semiconductor amplifying element, and wherein said first and second semiconductor amplifying elements comprise a pair of MOS transistors.

### Claim 2 (depends on 1)

A semiconductor integrated circuit according to claim 1, wherein said MOS transistors are of the same channel conductivity type.

### Claim 3 (depends on 1)

A semiconductor integrated circuit according to claim 1, wherein said MOS transistors are of opposite channel conductiveity type.

### Claim 4

A semiconductor integrated circuit comprising:
(1) an internal logic block including a plurality of C-MOS elements;
(2) an output terminal;
(3) an output buffer circuit connected between said internal logic circuit and said output terminal;
(4) a first power source terminal receptive of a ground potential as a first power source voltage; and
(5) a second power source terminal receptive of a negative voltage as a second power source voltage,
wherein said internal logic circuit and said output buffer circuit are operative with said negative voltage, wherein said output buffer circuit has an input terminal receptive of an output signal of said internal logic circuit, wherein said output buffer circuit includes means for generating an output signal at an ECL level at said output terminal in response to receiving the output signal of said internal logic circuit, wherein said means of said output buffer circuit includes an emitter-follower transistor having its emitter connected with said output terminal and its base responsive to the output signal of said internal logic circuit as well as a semiconductor amplifying element having its input electrode responsive to the output signal of said internal logic circuit and its output electrode connected through a load resistor with said ground potential so that the base of said emitter-follower transistor is driven by the signal of said output electrode of said semiconductor amplifying element, wherein said means of said output buffer circuit further comprises a second emitter-follower transistor having its emitter coupled with a second output terminal and its base coupled with a second semiconductor amplifying element, wherein said second semiconductor amplifying element is differentially coupled with said first semiconductor amplifying element, wherein said internal logic circuit provides first and second output signals to said output buffer circuit, and wherein said output buffer circuit includes a first switching element coupled between said first internal logic output signal and said first semiconductor amplifying element and a second switching element coupled between said second internal logic output signal and said first semiconductor amplifying element.

### Claim 5 (depends on 4)

A semiconductor integrated circuit according to claim 4, wherein said first and second switching elements are MOS transistors.

### Claim 6 (depends on 4)

A semiconductor integrated circuit according to claim 4, wherein said output buffer circuit further includes a NOR circuit and a third switching element, wherein said first and second internal logic output signals drive inputs of said NOR circuit, and wherein said third switching element of an MOS transistor is coupled between an output of said NOR circuit and said second semiconductor amplifying element.

### Claim 7

A semiconductor integrated circuit comprising:
(1) an internal logic block including a plurality of C-MOS elements;
(2) an output terminal;
(3) an output buffer circuit connected between said internal logic circuit and said output terminal;
(4) a first power source terminal receptive of a ground potential as a first power source voltage; and
(5) a second power source terminal receptive of a negative voltage as a second power source voltage,
wherein said internal logic circuit and said output buffer circuit are operative with said negative voltage, wherein said output buffer circuit has an input terminal receptive of an output signal of said internal logic circuit, wherein said output buffer circuit includes means for generating an output signal at an ECL level at said output terminal in response to receiving the output signal of said internal logic circuit, wherein said means of said output buffer circuit includes an emitter-follower transistor having its emitter connected with said output terminal and its base responsive to the output signal of said internal logic circuit as well as a semiconductor amplifying element having its input electrode responsive to the output signal of said internal logic circuit and its output electrode connected through a load resistor with said ground potential so that the base of said emitter-follower transistor is driven by the signal of said output electrode of said semiconductor amplifying element, wherein said means of said output buffer circuit further comprises a second emitter-follower transistor having its emitter coupled with a second output terminal and its base coupled with a second semiconductor amplifying element, wherein said second semiconductor amplifying element is differentially coupled with said first semiconductor amplifying element, wherein said first and second semiconductor amplifying elements comprise a pair of emitter-coupled bipolar transistors, wherein said output buffer circuit further includes first and second switching elements of MOS transistors as well as an inverter circuit, wherein said first switching element is responsive to the output signal of said internal logic circuit and coupled between said input electrode and said output electrode of said first semiconductor amplifying element, wherein an input terminal of said inverter circuit is responsive to the output signal of said internal logic circuit, and wherein said second switching element is responsive to an output signal of said inverter circuit and coupled between an input electrode and an output electrode of said second semiconductor amplifying element.

### Claim 8 (depends on 1)

A semiconductor integrated circuit according to claim 1, wherein said second semiconductor amplifying element is responsive to a reference voltage.

### Claim 9 (depends on 1)

A semiconductor integrated circuit according to claim 1, wherein said pair of MOS transistors are source-coupled to one another.

### Claim 10 (depends on 8)

A semiconductor integrated circuit according to claim 8, wherein said pair of MOS transistors are source-coupled to one another.

### Claim 11 (depends on 1)

A semiconductor integrated circuit according to claim 1, wherein a drain of one of said pair of MOS transistors is coupled to a source of the other of said pair of MOS transistors.

### Claim 12 (depends on 8)

A semiconductor integrated circuit according to claim 8, wherein a drain of one of said pair of MOS transistors is coupled to a source of the other of said pair of MOS transistors.

### Claim 13 (depends on 4)

A semiconductor integrated circuit according to claim 4, wherein said first and second semiconductor elements comprise a pair of emitter-coupled bipolar transistors.

### Claim 14 (depends on 4)

A semiconductor integrated circuit according to claim 4, wherein said second semiconductor element is responsive to a reference source.