Digital data processor incorporating an orthogonally connected logic cell array
AssigneeThe Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and Northern Ireland
InventorsJohn V. McCanny, John G. McWhirter
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Abstract
The invention provides a digital data processor which has been systemetized down to bit level. The processor includes a regular array of identical processing cells which perform a logic operation on incoming bits. The cells repeatedly perform a cell operation under the control of clocks which govern the inputting to and outputting from the cell of data bits. Each bit takes part in a maximum of one cell operation in one repetition of the clock having the highest repetition frequency. Processing cell arrays for dealing with larger numbers may be readily built up from smaller arrays used for smaller numbers. Having obtained a fully working design for one type of processing cell, the full array consisting of a plurality of cells is proven.
Claims10
A digital data processor for performing a multiplication operation involving generation and accumulation of bit-level product terms, and including:
- (1) a two dimensional array of bit level arithmetic logic cells arranged in rows and columns, each cell being arranged to receive input multiplicand, carry and cumulative sum bits and output new carry and cumulative sum bits;
- (2) a plurality of storing means each arranged for input and subsequent output of successive bits from a respective cell output in response to clock signal activation;
- (3) cell interconnection lines arranged to connect each cell via respective storing means to its immediate row and column neighbors, said lines providing routes through the array for propagation of all input multiplicand bits;
- (4) digital data input means for multiplicand input to the array in response to clock signal activation, said input means being arranged to provide input data with relative delays;
- (5) clocking means for sole control of calculation execution, the clocking means being arranged to activate the storing means and digital data input means appropriately to synchronize input of successive combinations of bits to each cell, and the storing means, cell interconnection lines, digital data input means and clocking means being arranged in combination so that cumulative sum contributions to output results are accumulated in cascade along routes through the array via successive logic cells;
- (6) array output lines connected to respective cell outputs appropriate to provide cumulative sums resulting from cell logic operations cascaded through the array.
Dependencies are inferred from the claim text.