Method of making thyristor with a high tolerable bias voltage

A process for fabricating a thyristor, comprising the steps of:

• preparing a silicon semiconductor substrate by a modified Czochralski process wherein an ingot of single-crystal silicon is pulled up with a magnetic field applied in a direction perpendicular to to the convection of molten silicon, said ingot being pulled up in a manner such that the temperature at the interface between the molten silicon and the ingot is higher in the central area than at the periphery;
• diffusing an impurity of a second conductivity type into upper and lower surfaces of said semiconductor substrate, said substrate being of a first conductivity type and having a higher impurity concentration at a central area than at any other area thereof so as to form a second base layer of the second conductivity type on the upper surface and a first emitter layer of the second conductivity type on the lower surface, with that region sandwiched between said second base layer and said first emitter layer forming a first base layer;
• and
• diffusing an impurity of the first conductivity type from the upper surface of said substrate to form a second emitter layer which covers all but a gate region of the upper surface and is situated within the area defined by the second base layer, the surface of the gate region of the second base layer being exposed on said upper surface and including said central area.

A process for fabricating a thyristor, comprising the steps of:

• preparing a silicon semiconductor substrate from a wafer fabricated by a floating zone process and exposed to neutron irradiation, the central area of the wafer being exposed to a higher dose of neutron radiation than the peripheral area thereof,
• diffusing an impurity of a second conductivity type into upper and lower surfaces of said semiconductor substrate, said substrate being of a first conductivity type and having a higher impurity concentration at a central area than at any other area thereof so as to form a second base layer of the second conductivity type on the upper surface and a first emitter layer of the second conductivity type on the lower surface, with that region sandwiched between said second base layer and said first emitter layer forming a first base layer;
• and
• diffusing an impurity of the first conductivity type from the upper surface of said substrate to form a second emitter layer which covers all but a gate region of the upper surface and is situated within the area defined by the second base layer, the surface of the gate region of the second base layer being exposed on said upper surface and including said central area.