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US 4,638,300 AGranted
Central processing unit having built-in BCD operation
AssigneeAdvanced Micro Devices, Inc.
InventorMichael J. Miller
Life of this patent
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AssigneeAdvanced Micro Devices, Inc.
InventorMichael J. Miller
Estimating the term…
A CPU data path portion having an ALU, an adjuster unit, a shifter unit and a shift register unit is disclosed. The CPU is capable of selectively forming the sum or difference of a first BCD operand and a second BCD operand by arithmetically combining the operands with the ALU to form binary results, the results dependent upon the arithmetic operation selected and adjusting the results with the adjuster unit into BCD, the adjustment also dependent upon the arithmetic operation selected. The CPU is further capable of selectively converting an operand from binary to BCD format or from BCD to binary format by iteratively shifting the operand between the shifter unit and the shift register unit and correcting the operand with the ALU, the direction of the shift and the ALU correction dependent upon the conversion selected.
In a circuit for converting binary digital signals into BCD digital signals by correcting and shifting said binary signals iteratively, an ALU for correcting said binary digital signals comprising:
In a circuit for converting BCD digital signals into binary digital signals by shifting and correcting said BCD digital signals iteratively, an ALU for correcting said BCD digital signals comprising:
In a circuit for selectively converting digital signals from binary into BCD or BCD into binary by shifting and correcting said digital signals iteratively, an ALU for correcting said digital signals, said ALU comprising
A data path of a CPU having an ALU, a shifter responsive to ALU output signals, means for transferring shifter output signals to said ALU as input signals for iterative operations, and a shift register means accepting signals shifted out from said shifter and shifting out signals to said shifter, for selectively converting digital signals representing a number from binary to BCD or BCD into binary by iteratively shifting said signals between said shifter and said shift register means and correcting said digital signals with said ALU, said ALU comprising
A CPU having an ALU, an adjuster unit, a shifter unit and a shift register unit, said CPU capable of selectively forming the sum or difference of a first BCD operand and and a second BCD operand by arithmetically combining said BCD operands with said ALU to form results in binary, said ALU results dependent upon the arithmetic operation selected, and adjusting said binary ALU results with said adjuster unit into BCD format, said adjustment dependent upon the arithmetic operation selected;
Dependencies are inferred from the claim text.