US 4,635,354 A · Low cost electronic apparatus construction method · patentgrep

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Abstract

The present invention is a low cost electronic apparatus construction method which may be employed for hand held calculators, electronic learning aids and electronic games. This technique involves a simplification in the construction of the apparatus including reduction in the number of piece parts necessary for the assembly. The primary electrical circuit interconnection pattern of the electronic apparatus is printed upon a part of the case of the apparatus which must be nonconducting. This printed circuit pattern together with the construction of the back case includes connection portions for electrical connection to the major components of the apparatus which may include an integrated circuit, a display device and an electrical power source. The primary circuit pattern printed on the back case includes a plurality of interleaved comb key switch positions. The keyboard is constructed employing a plurality of keys aligned in registration with the key switch portions, each key having a shorting bar for causing electrical connection across the key switch portion when the key is depressed. The top case of the apparatus has an aperture for viewing the display device and a plurality of apertures for the keys. In an alternative embodiment, this top case also includes an aperture enabling light to shine on a photovoltaic power cell employed to generate the electric power needed to operate the apparatus.

Claims14

Dependent claims

A method for manufacture of an electronic apparatus comprising the steps of:

forming a first case part for said electronic apparatus having a non-conducting interior surface;
forming a conductive interconnection pattern on said non-conducting interior surface, said conductive interconnection pattern having at least one set of connection conductors including a plurality of conductors arranged in proximity about a predetermined region of said non-conducting interior surface and having a plurality of key switch positions, each key switch position having two conductors in proximity;
applying conductive adhesive material to said connection conductors of said set of connection conductors of said interconnection pattern at respective locations thereon in proximity to said predetermined region of said non-conducting interior surface;
disposing an integrated circuit semiconductor device having a plurality of outwardly extending leads within said predetermined region of said non-conducting interior surface with said leads extending outwardly of said predetermined region in spaced relation with said non-conducting interior surface of said first case part on which said conductive interconnection pattern is formed;
aligning the leads of said integrated circuit semiconductor device in registering partially overlapping spaced relationship with said set of connection conductors of said interconnection pattern so as to position the leads of said integrated circuit semiconductor device in respective abutment with the conductive adhesive material on the corresponding connection conductors of said set of connection conductors of said interconnection pattern such that said leads of said integrated circuit semiconductor device are electrically coupled to said set of connection conductors of said interconnection pattern in response to disposing said integrated circuit semiconductor device within said predetermined region of said non-conducting interior surface;
forming a second case part for said electronic apparatus having a plurality of keyholes therein positioned in registration with said plurality of key switch positions of said interconnection pattern;
disposing a key in each of said keyholes of said second case part, each key having a conductive portion for shorting together said two proximate conductors of a corresponding key switch position of said interconnection pattern and having a biasing means for normally preventing such shorting;
and
coupling together said first case part and said second case part.

6 more elements

A method for manufacture of an electronic apparatus comprising the steps of:

forming a first case part for electronic apparatus having a non-conducting interior surface provided with a depression therein for accommodating an integrated circuit semiconductor device;
forming a conductive interconnection pattern on said non-conducting interior surface, said conductive interconnection pattern having first, second and third sets of connection conductors, each set including a plurality of conductors, said first set of connection conductors being disposed in proximity to said depression and having a plurality of key switch positions, each key switch position having two conductors in proximity;
applying conductive adhesive material to at least said connection conductors of said first set of connection conductors of said interconnection pattern at respective locations thereon in proximity to said depression;
disposing an integrated circuit semiconductor device having a plurality of outwardly extending leads at least partially within said depression with said leads extending outwardly of said depression into spaced relation with said non-conducting interior surface of said first case part on which said conductive interconnection pattern is formed;
aligning the leads of said integrated circuit semiconductor device in registering partially overlapping spaced relationship with said first set of connection conductors of said interconnection pattern so as to position the leads of said integrated circuit semiconductor device in respective abutment with the conductive adhesive material on the corresponding connection conductors of said first set of connection conductors of said interconnection pattern such that said leads of said integrated circuit semiconductor device are electrically coupled to said first set of connection conductors of said interconnection pattern in response to disposing said integrated circuit semiconductor device at least partially within said depression by virtue of the relative dimensions of said integrated circuit semiconductor device and said depression;
electrically coupling an output device to said second set of connection conductors of said interconnection pattern;
electrically coupling a power source to said third set of connection conductors of said interconnection pattern;
forming a second case part for said electronic apparatus having an opening therein positioned for registration with said output device and a plurality of keyholes therein positioned for registration with said plurality of key switch positions of said interconnection pattern;
disposing a key in each of said keyholes of said second case part, each key having a conductive portion for shorting together said two proximate conductors of a corresponding key switch position of said interconnection pattern and having a biasing means for normally preventing such shorting;
and
coupling together said first case part and said second case part.

8 more elements

A method for manufacture of an electronic apparatus comprising the steps of:

forming a first case part for said electronic apparatus having a non-conducting interior surface provided with a depression therein for accommodating an output device;
forming a conductive interconnection pattern on said non-conducting interior surface, said conductive interconnection pattern having first, second and third sets of connection conductors, each set including a plurality of conductors, said first set of connection conductors having a plurality of key switch positions, each key switch position having two conductors in proximity, and said second set of connection conductors being disposed in proximity to said depression;
applying conductive adhesive material to at least said connection conductors of said first and second sets of connection conductors of said interconnection pattern at respective locations thereon, the conductive adhesive material being applied to said second set of connection conductors at locations in proximity to said depression;
disposing an integrated circuit semiconductor device having a plurality of outwardly extending leads within a predetermined region of said non-conducting interior surface with said leads extending outwardly of said predetermined region into spaced relation with said non-conducting interior surface of said first case part on which said conductive interconnection pattern is formed;
aligning the leads of said integrated circuit semiconductor device in registering partially overlapping spaced relationship with said first set of connection conductors of said interconnection pattern so as to position the leads of said integrated circuit semiconductor device in respective abutment with the conductive adhesive material on the corresponding connection conductors of said first set of connection conductors of said interconnection pattern such that said leads of said integrated circuit semiconductor device are electrically coupled to said first set of connection conductors of said interconnection pattern;
disposing an output device having leads at least partially within said depression with the leads extending outwardly of the depression into spaced relation with said non-conducting interior surface of said first case part on which said conductive interconnection pattern is formed;
aligning the leads of said output device in registering partially overlapping spaced relationship with said second set of connection conductors of said interconnection pattern so as to position the leads of said output device in respective abutment with the conductive adhesive material on the corresponding connection conductors of said second set of connection conductors of said interconnection pattern such that said leads of said output device are electrically coupled to said second set of connection conductors of said interconnection pattern in response to disposing said output device at least partially within said depression by virtue of the relative dimensions of said output device and said depression;
electrically coupling a power source to said third set of connection conductors of said interconnection pattern;
forming a second case part for said electronic apparatus having an opening therein positioned for registration with said output device and a plurality of keyholes therein positioned for registration with said plurality of key switch positions of said interconnection pattern;
p1 disposing a key in each of said keyholes of said second case part, each key having a conductive portion for shorting together said two proximate conductors of a corresponding key switch position of said interconnection pattern and having a biasing means for normally preventing such shorting;
and
coupling together said first case part and said second case part.

9 more elements

A method for manufacture of an electronic apparatus comprising the steps of:

forming a first case part for said electronic apparatus having
non-conducting interior surface provided with a depression therein for accommodating an integrated circuit semiconductor device;
forming a conductive interconnection pattern on said non-conducting interior surface, said conductive interconnection pattern having first, second and third sets of connection conductors, each set including a plurality of conductors, said first set of connection conductors being disposed in proximity to said depression and having a plurality of key switch positions, each key switch position having two conductors in proximity;
applying conductive adhesive material to at least said connection conductors of said first set of connection conductors of said interconnection pattern at respective locations thereon in proximity to said depression;
forming a circuit pattern on a circuit board, said circuit pattern having first and second connection conductors;
providing an integrated circuit semiconductor device having a plurality of leads extending upwardly therefrom;
mounting said circuit board on said integrated circuit semiconductor device by electrically coupling the leads of said integrated circuit semiconductor device to said first connection conductors of said circuit board;
disposing said integrated circuit semiconductor device at least partially within said depression with said circuit board mounted thereon so as to dispose said second connection conductors of said circuit board in spaced relation with non-conducting interior surface of said first case part on which said conductive interconnection pattern is formed;
aligning said second connection conductors of said circuit board in registering partially overlapping spaced relationship with said first set of connection conductors of said interconnection pattern so as to position said second connection conductors of said circuit board in respective abutment with the conductive adhesive material on the corresponding connection conductors of said first set of connection conductors of said interconnection pattern such that said second connection conductors of said circuit board are electrically coupled to said first sert of connection conductors of said interconnection pattern;
electrically coupling an output device to said second set of connection conductors of said interconnection pattern;
electrically coupling a power source to said third set of connection conductors of said interconnection pattern;
forming a second case part for said electronic apparatus having an opening therein positioned for registration with said output device and a plurality of keyholes therein positioned for registration with said plurality of key switch positions of said interconnection pattern;
disposing a key in each of said keyholes of said second case part, each key having a conductive portion for shorting together said two proximate conductors of a corresponding key switch position of said interconnection pattern and having a biasing means for normally preventing such shorting;
and
coupling together said first case part and said second case part.

12 more elements

A method for manufacture of an electronic apparatus comprising the steps of:

forming an exterior case for said electronic apparatus having at least one non-conducting interior surface provided with a depression therein for accommodating an integrated circuit semiconductor device;
forming a conductive interconnection pattern on said non-conducting interior surface, said conductive interconnection pattern having first, and second and third sets of connection conductors, each set including a plurality of conductors, said first set of connection conductors being disposed in proximity to said depression;
applying conductive adhesive material to at least said connection conductors of said first set of connection conductors of said interconnection pattern at respective locations thereon in proximity to said depression;
disposing an integrated circuit semiconductor device having a plurality of outwardly extending leads at least partially within said depression with said leads extending outwardly of said depression into spaced relation with said non-conducting interior surface of said case on which said conductive interconnection pattern is formed;
aligning the leads of said integrated circuit semiconductor device in registering partially overlapping spaced relationship with said first set of connection conductors of said interconnection pattern so as to position the leads of said integrated circuit semiconductor device in respective abutment with the conductive adhesive material on the corresponding connection conductors of said first set of connection conductors of said interconnection pattern such that said leads of said integrated circuit semiconductor device are electrically coupled to said first set of connection conductors of said interconnection pattern in response to disposing said integrated circuit semiconductor device at least partially within said depression by virtue of the relative dimensions of said integrated circuit semiconductor device and said depression;
electrically coupling an output device to said second set of connection conductors of said interconnection pattern;
and
electrically coupling a power source to said third set of connection conductors of said interconnection pattern.

5 more elements

A method for manufacture of an electronic apparatus comprising the steps of:

forming an exterior case for said electronic apparatus having at least one non-conducting interior surface provided with a depression therein for accommodating an output device;
forming a conductive interconnection pattern on said non-conducting interior surface, said conductive interconnection pattern having first, second and third sets of connection conductors, each set including a plurality of conductors, said second set of connection conductors being disposed in proximity to said depression;
applying conductive adhesive material to at least said connection conductors of said first and second sets of connection conductors of said interconnection pattern at respective locations thereon, the conductive adhesive material being applied to said second set of connection conductors at locations in proximity to said depression;
disposing an integrated circuit semiconductor device having a plurality of outwardly extending leads within a predetermined region of said non-conducting interior surface with said leads extending outwardly of said predetermined region into spaced relation with said non-conducting interior surface of said case on which said conductive interconnection pattern is formed;
aligning the leads of said integrated circuit semiconductor device in registering partially overlapping spaced relationship with said first set of connection conductors of said interconnection pattern so as to position the leads of said integrated circuit semiconductor device in respective abutment with the conductive adhesive material on the corresponding connection conductors of said first set of connection conductors of said interconnection pattern such that said leads of said integrated circuit semiconductor device are electrically coupled to said first set of connection conductors of said interconnection pattern;
disposing an output device having leads at least partially within said depression with the leads extending outwardly of the depression into spaced relation with said non-conducting interior surface of said case on which said conductive interconnection pattern is formed;
aligning the leads of said output device in registering partially overlapping spaced relationship with said second set of connection conductors of said interconnection pattern so as to position the leads of said output device in respective abutment with the conductive adhesive material on the corresponding connection conductors of said second set of connection conductors of said interconnection pattern such that said leads of said output device are electrically coupled to said second set of connection conductors of said interconnection pattern in response to disposing said output device at least partially within said depression by virtue of the relative dimensions of said output device and said depression;
and
electrically coupling a power source to said third set of connection conductors of said interconnection pattern.

6 more elements

A method for manufacture of an electronic apparatus comprising the steps of:

forming an exterior case for said electronic apparatus having at least one non-conducting interior surface provided with a depression therein for accommodating an integrated circuit semiconductor device;
forming a conductive interconnection pattern on said non-conducting interior surface, said conductive interconnection pattern having first, second and third sets of connection conductors, each set including a plurality of conductors, said first set of connection conductors being disposed in proximity to said depression;
applying conductive adhesive material to at least said connection conductors of said first set of connection conductors of said interconnection pattern at respective locations thereon in proximity to said depression;
forming a circuit pattern on a circuit board, said circuit pattern having first and second connection conductors;
providing an integrated circuit semiconductor device having a plurality of leads extending upwardly therefrom;
mounting said circuit board on said integrated circuit semiconductor device by electrically coupling the leads of said integrated circuit semiconductor device to said first connection conductors of said circuit board;
disposing said integrated circuit semiconductor device at least partially within said depression with said circuit board mounted thereon so as to dispose said second connection conductors of said circuit board in spaced relation with said non-conducting interior surface of said case on which said conductive interconnection pattern is formed;
aligning said second connection conductors of said circuit board in registering partially overlapping spaced relationship with said first set of connection conductors of said interconnection pattern so as to position said second connection conductors of said circuit board in respective abutment with the conductive adhesive material on the corresponding connection conductors of said first set of connection conductors of said interconnection pattern such that said second connection conductors of said circuit board are electrically coupled to said first set of connection conductors of said interconnection pattern;
electrically coupling an output device to said second set of connection conductors of said interconnection pattern;
and
electrically coupling a power source to said third set of connection conductors of said interconnection pattern.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 06/702,755Filed 19 Feb 1985 · continuation
Priority: 22 Jul 1982
Granted: 13 Jan 1987
Term ends: Not estimatedThe source records don’t support an estimate.

Classification42 codes

H05K 3/321
Electrically connecting electric components or wires to printed circuits: by conductive adhesives
G06F 15/0216
Manually operated with input through keyboard and computation using a built-in program, e.g. pocket calculators: constructional details or…
H01H 13/702
Having a plurality of operating members associated with different sets of contacts, e.g. keyboard: with contacts carried by or formed from layers…
H05K 1/0284
Details: details of three-dimensional rigid printed circuit boards

Family

Serial401,053Parent of this continuation · filed 22 Jul 1982
US 4,635,354 AThis patent

From the US filing history. Foreign family members aren’t listed.

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