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AssigneeFairchild Semiconductor Corporation
InventorsJohn Schinabeck, James R. Murdock
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A plurality of test signal applying and response signal monitoring circuits is coupled to pins of an electronic device being tested to force test stimuli signals onto input pins of the device under test. The response signals are monitored while the device is being tested. Each test signal applying and response signal monitoring circuit includes a node to be coupled to a pin of the device under test, a digitally programmed source for supplying a test signal connectable to the node by a first switch, and a comparison circuit connected to the node by a second switch for indicating the relative magnitude of the response signal with respect to a programmed reference level on a repetitive basis during testing to increase test rate. Other features are also disclosed.
A method for repeatedly monitoring the response signal at a node of a deivce under test caused by a test signal applied to the node by digitally programmed source means switchably connected by a first switch means to the node and comparison means switchably connected by a second switch means to the node, the method comprising the steps of:
Apparatus for applying a test signal to and monitoring a response signal at a node of a device under test, comprising:
A method for repeatedly monitoring the response signal at a node of a device under test caused by a test signal applied to the node by digitally programmed source means having a preselected programmed voltage-current characteristic defined by not-to-exceed voltage rail and current rail levels switchably connected by a first switch means to the node and comparison means switchably connected by a second switch means to the node, the method comprising the steps of:
Apparatus for repeatedly monitoring the response signal at a node of a device under test caused by a test signal applied to the node, comprising:
Dependencies are inferred from the claim text.