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US 4,634,998 AGranted
Fast phase-lock frequency synthesizer with variable sampling efficiency
AssigneeHughes Aircraft Company
InventorJames A. Crawford
Life of this patent
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Abstract
A phase-locked frequency synthesizer (10) having a voltage controlled oscillator (40), a divider circuit (60), and a sample-and-hold phase detector (30, 80, 90, 100, 110) which includes sample-and-hold circuitry (FIG. 6) having variable efficiency. Specifically, the sample-and-hold circuitry provides a sampling pulse of variable width which is controlled to be wider during acquisition and narrower during steady-state operation.
Claims11
A phase-locked frequency synthesizer comprising:
- a voltage controlled oscillator (VCO) for providing an output signal having a selectable output frequency;
- divider means responsive to said VCO output signal for dividing by a division ratio N and for providing a divide-by-N signal, said VCO output frequency being related to said division ratio N;
- ramp generating means for providing a ramp signal;
- means for providing a reference frequency signal;
- means for starting said ramp signal in response to said reference frequency signal and for stopping the ramp signal in response to said divide-by-N signal;
- and
- sample-and-hold means having variable efficiency for sampling the ramp signal in response to said divide-by-N signal to provide a sampled signal for controlling said voltage controlled oscillator.
4 more elements
A phase-locked frequency synthesizer comprising:
- a voltage controlled oscillator (VCO) for providing an output signal having a selectable output frequency which is related to a division ratio N;
- divider means responsive to said VCO output signal for dividing by said division ratio N and for providing a divide-by-N signal;
- ramp generating means for providing a ramp signal;
- means for providing a reference frequency signal;
- means for starting said ramp signal in response to said reference frequency signal and for stopping the ramp signal in response to said divide-by-N signal;
- and
- sample-and-hold means having a variable sample time for sampling said ramp signal in response to said divide-by-N signal to provide a sampled voltage signal for controlling said voltage controlled oscillator, said variable sample time being longer for phase-lock acquisition and being shorter for steady-state operation.
4 more elements
Dependencies are inferred from the claim text.