Sewing machine with memory input reconfiguration based on type of memory being used
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorKatsunori Shigeta
Life of this patent
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Abstract
An apparatus for controlling a sewing machine includes a control circuit having connector lines for reading data from a semiconductor memory device and a switching circuit for automatically switching the connector lines dependent on the type of the semiconductor memory device employed by reading a keyword stored at a head address in the semiconductor memory device. The control apparatus can use any type of semiconductor memory device available at the present time and in the future. The switching circuit includes a logic circuit which can be implemented by a simple gating circuit.
Claims5
An apparatus for controlling a sewing machine, comprising:
- (a) a semiconductor memory device having sewing pattern data and an identification code related to a type of said semiconductor memory device stored therein;
- (b) a control circuit for reading the sewing pattern data from said semiconductor memory device to control the sewing machine for effecting a predetermined sewing operation, said control circuit including connector lines for reading the sewing pattern data from said semiconductor memory device;
- and
- (c) a switching circuit for automatically switching connections of said connector lines dependent on the type of said semiconductor memory device by reading said identification code from said semiconductor memory device to determine the type thereof and for effecting logic connections of said connector lines suitable for said type of said semiconductor memory device.
A method of controlling operation of a sewing machine, comprising the following steps:
- (i) issuing switching signals along first switching signal lines from a control circuit, indicative of a particular type of memory device, to a logic circuit connected via first address lines, first data lines, and first control signal lines, to said control circuit, and via second address lines, second data lines, and second control signal lines, to a semiconductor memory device;
- (ii) configuring said first address lines, first data lines, and first control signal lines, for receiving address information and data from said particular type of memory device, in response to said switching signals;
- and
- (iii) if said semiconductor memory device is of said particular type, receiving an identification code from said semiconductor memory device and subsequently transferring pattern data from said semiconductor memory device to said control circuit;
- or
- (iv) if said semiconductor memory device is not of said particular type, repeating steps (i) and (ii) with different switching signals indicative of a different type of memory device, step (ii) then comprising the step of configuring said logic circuit to receive address information and data from said different type of semiconductor memory device, until said logic circuit is configured to receive address information and data from said semiconductor memory device;
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- (v) receiving said identification code from said semiconductor device, and subsequently transferring pattern data from said semiconductor memory device to said control circuit.
Dependencies are inferred from the claim text.