Merging of logic function circuits to ECL latch or flip-flop circuit

A combination multiplexer and latch circuit formed of a latch circuit portion and a multiplexer circuit portion which is fabricated as a single gate on an integrated semiconductor chip, said combination circuit comprising:

• the latch circuit portion including a pair of first and second latch transistors whose emitters are commonly connected together;
• the bases of said first and second latch transistors being coupled to receive input signals from a multiplexer circuit portion;
• a latch enable transistor having its collector tied to the common emitters of said first and second latch transistors, its emitter connected to a first current source, and its base connected to a latch enable terminal;
• a first output transistor having its base connected to the collector of said first latch transistor, its collector connected to a supply potential and its emitter coupled to a true output signal terminal;
• a second output transistor having its base connected to the collector of said second latch transistor, its collector connected to the supply potential and its emitter coupled to a complementary output signal terminal;
• the emitter of said first output transistor being connected to the base of said second latch transistor and to a second current source and the emitter of said second output transistor being connected to the base of said first latch transistor and to a third current source;
• and
• the multiplexer circuit portion having its outputs coupled to the bases of said first and second latch transistors of said latch circuit portion to provide the input signals.

A combination EXCLUSIVE OR and latch circuit formed as a single gate on an integrated circuit semiconductor chip, said combination circuit comprising:

• a latch circuit portion including a pair of first and second latch transistors whose emitters are commonly connected together;
• the bases of said first and second latch transistors being coupled to receive input signals form an EXCLUSIVE OR circuit portion;
• a latch enable transistor having its collector tied to the common emitters of said first and second latch transistors, its emitter connected to a first current source and its base connected to a latch enable terminal;
• a first output transistor having its base connected to the collector of said first latch transistor, its collector connected to a supply potential and its emitter coupled to a true output signal terminal;
• a second output transistor having its base connected to the collector of said second latch transistor, its collector connected to the supply potential and its emitter coupled to a complementary output signal terminal;
• the emitter of said first output transistor connected to the base of said latch transistor and to a second current source and the emitter of said second output transistor being connected to the base of said first latch transistor and to a third current source;
• and
• the EXCLUSIVE OR circuit portion having its outputs coupled to the bases of said first and second latch transistors to provide the input signals.