US 4,621,317 AGranted

Arithmetic logic unit of a sequence controller

AssigneesHitachi, Ltd., Nissan Motor Co., Ltd.

InventorsToichi Kudo, Takasi Abe, Seiichiro Ogawa

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Abstract

An arithmetic logic unit for a stored program sequence controller stores a program equivalent to a relay sequence in a program memory and executes sequence control in accordance with the stored program. A first push-down storage register for sequentially storing logical operation results at branch start points of the relay sequence and a second push-down storage register for sequentially storing logical operation results for branches connected to the branch points based on the logical operation results stored in the first push-down storage register are provided. The arithmetic logic unit carries out the operations based on the logical operation results stored in the first and second push-down storage registers.

Claims5

Dependent claims

An arithmetic logic unit of a sequence controller having an input/output circuit for providing logic status signals of selected input elements and output signals to selected output elements, and program memory means for storing a sequence program equivalent to a relay sequence having one or more branches for executing sequence control in accordance with the stored sequence program, wherein said sequence program is constituted by a combination of first instructions relating to connection status indicating a start point, a branch start point, a branch continuation, a branch end point and a branch junction point provided in the relay sequence, and second instructions indicating input and output elements provided in the relay sequence;

said arithmetic logic unit comprising:
an accumulator for successively storing intermediate results of logical operations and output signals for application to said input/output circuit;
a first push-down register and a second push-down register each capable of shifting bidirectionally and each having a common inlet/outlet for a signal;
and
operation control means connected to said accumulator, said program memory means and said first and second push-down registers, and being
(1) responsive to an instruction indicating the start point for shifting a logic signal of a predetermined initial status into said first push-down register;
(2) responsive to an instruction indicating the branch start point for shifting the content stored at that time in said accumulator into said first push-down register;
(3) responsive to an instruction indicating the branch continuation or the branch end point for shifting the content of said accumulator into said second push-down register;
(4) responsive to an instruction indicating the branch continuation followed by an input element for performing a logical AND operation of the output signal from said first push-down register and a selected logical status signal of an input element without a shifting operation of said first push-down register and then storing the AND operation result into said accumulator;
(5) responsive to an instruction indicating the branch end point followed by an input element for performing a logical AND operation of the output signal from said first push-down register and the logical status signal of a selected input element by means of an output shifting operation of said first push-down register followed by storing the AND operation result into said accumulator;
(6) responsive to an instruction indicating the branch continuation followed by an output element for storing the output content from said first push-down register into said accumulator without a shifting operation of said first push-down register;
(7) responsive to an instruction indicating the branch end point followed by an output element for storing the output content from said first push-down register into said accumulator by means of an output shifting operation of said first push-down register;
and
(8) responsive to the instruction indicating the branch junction point for performing a logical OR operation of the output signal from said second push-down register and the content of said accumulator by means of an output shifting operation of said second push-down register followed by storing the OR operation result into said accumulator;
and
(9) responsive to an instruction indicating an output element for outputting the content of said accumulator to a corresponding output element via said input/output circuit.

13 more elements

Dependencies are inferred from the claim text.

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Abstract

said arithmetic logic unit comprising:
an accumulator for successively storing intermediate results of logical operations and output signals for application to said input/output circuit;
a first push-down register and a second push-down register each capable of shifting bidirectionally and each having a common inlet/outlet for a signal;
and
operation control means connected to said accumulator, said program memory means and said first and second push-down registers, and being
(1) responsive to an instruction indicating the start point for shifting a logic signal of a predetermined initial status into said first push-down register;
(2) responsive to an instruction indicating the branch start point for shifting the content stored at that time in said accumulator into said first push-down register;
(3) responsive to an instruction indicating the branch continuation or the branch end point for shifting the content of said accumulator into said second push-down register;
(4) responsive to an instruction indicating the branch continuation followed by an input element for performing a logical AND operation of the output signal from said first push-down register and a selected logical status signal of an input element without a shifting operation of said first push-down register and then storing the AND operation result into said accumulator;
(5) responsive to an instruction indicating the branch end point followed by an input element for performing a logical AND operation of the output signal from said first push-down register and the logical status signal of a selected input element by means of an output shifting operation of said first push-down register followed by storing the AND operation result into said accumulator;
(6) responsive to an instruction indicating the branch continuation followed by an output element for storing the output content from said first push-down register into said accumulator without a shifting operation of said first push-down register;
(7) responsive to an instruction indicating the branch end point followed by an output element for storing the output content from said first push-down register into said accumulator by means of an output shifting operation of said first push-down register;
and
(8) responsive to the instruction indicating the branch junction point for performing a logical OR operation of the output signal from said second push-down register and the content of said accumulator by means of an output shifting operation of said second push-down register followed by storing the OR operation result into said accumulator;
and
(9) responsive to an instruction indicating an output element for outputting the content of said accumulator to a corresponding output element via said input/output circuit.

13 more elements