Arithmetic logic unit for floating point data and/or fixed point data

An arithmetic logic unit for floating point data and fixed point data, comprising:

• first means for selectively providing a first pair of first and second floating point data which are to be mutually added, or a second pair consisting of third floating point data including a mantissa part into which fixed point data is provided and an exponent part having a value of zero and fourth floating point data including a mantissa part having a value of zero and an exponent part of a predetermined value;
• adjusting means connected to said first means for adjusting the first or second pair of floating point data provided by said first means to provide for each data of the selected pair an exponent part having the same value and two adjusted mantissa parts;
• adding means connected to said adjusting means for adding the two adjusted mantissa parts;
• shifting means connected to said adding means for shifting the output of said adding means;
• second means connected to said shifting means for controlling said shifting means to effect a shift by an amount depending on the output of said adding means, to normalize the output of said adding means;
• and
• third means connected to said second means and said adjusting means for providing a normalized exponent by modifying the exponent part provided from said adjusting means by an amount corresponding to said shift amount to normalize the exponent part of the sum of the data pair;
• whereby said shifting means and said third means provide respectively a normalized mantissa part and a normalized exponent part of either the sum of the first pair of data or a floating point data corresponding to the fixed point data.

An arithmetic logic unit for floating point data and fixed point data, comprising:

• input means for selectively providing, respectively, on first and second multiconductor input lines, either first and second floating point data or first and second fixed point data which are provided on respective conductors of the first and second input lines on which conductors mantissa parts of the first and second floating point data are respectively provided;
• comparing means connected to said input means for comparing exponent parts of the first and second input lines to provide a comparison signal which shows which of the exponent parts is larger and to provide a difference signal indicating the difference therebetween;
• first shifting means connected to said input means and said comparing means for shifting a mantissa part on one of said first and second input lines selected by the comparison signal by a first shift amount depending on the value of said difference signal;
• first prohibiting means connected to said shifting means for prohibiting the shifting operation of said first shifting means in response to a first signal;
• selecting means connected to said input means and said comparing means for selecting an exponent part on the other of the first and second input lines in response to said comparison signal;
• adding means connected to said shifting means and said input means for adding the shifted mantissa part from said first shifting means and the mantissa part on the other of said first and second input lines;
• second shifting means connected to said adding means for shifting an output of the adding means;
• detecting means connected to said adding means for detecting a second shift amount which is necessary for normalization of the output of the adding means, depending on the output of the adding means to control said second shifting means;
• second prohibiting means for prohibiting the shifting operation of said second shifting means in response to a second signal;
• means for modifying the selected exponent data by an amount depending upon said second shift amount to normalize the selected exponent data;
• and
• means for providing said first and second signals to said first and second prohibiting means, respectively, when said input means provides said first and second fixed point data.

An arithmetic logic unit for floating point data and fixed point data, comprising:

• first means for selectively providing a first pair of first and second floating point data which are to be subjected to an arithmetic operation to provide an arithmetic result or a second pair consisting of third floating point data which is to be converted to fixed point data and fourth floating point data which is a reference data for the conversion;
• adjusting means connected to said first means for adjusting the first or second pair of floating point data provided by said first means to provide for each data of the selected pair an exponent part having the same value and two adjusted mantissa parts;
• adding means connected to said adjusting means for adding the two adjusted mantissa parts;
• shifting means connected to said adding means for shifting the output of the adding means;
• second means connected to said shifting means for controlling said shifting means so that the output of said adding means either is not shifted by the shifting means or is shifted by a shift amount necessary for normalization of the output of said adding means, depending upon whether or not a control signal is provided to the second means, said shift amount being determined depending upon the output of the adding means;
• control means connected to said first means and said second means for providing said control signal to said second means when said first means selectively provides at its output the second pair of data;
• and
• third means connected to said second means and said adjusting means for providing a normalized exponent by modifying the exponent part provided from said adjusting means by an amount corresponding to said shift amount, to provide a normalized exponent part of the operated result of the data pair;
• whereby said shifting means and said third means respectively provide a normalized mantissa part and a normalized exponent part for an operational result of the first pair of the floating point data, when the first pair are selectively provided by said first means, and the shifting means provides the fixed point data corresponding to the third floating point data, when the second pair of floating point data are selectively provided by said first means.

An arithmetic logic unit for floating point data and fixed point data, comprising:

• first means for selectively providing a first pair of first and second floating point data which are to be subjected to an arithmetic operation or a second pair consisting of fixed point data which is to be converted to floating point data and third floating pointing data which is a reference data for the conversion;
• adjusting means connected to said first means for adjusting the first or second pair of floating point data provided by said first means to provide for each data of the selected pair an exponent part having the same value and two adjusted mantissa parts;
• adding means connected to said adjusting means for adding the two adjusted mantissa parts;
• shifting means connected to said adding means for shifting the output of said adding means;
• second means connected to said shifting means for controlling said shifting means to effect a shift by an amount depending on the output of said adding means, to normalize the output of said adding means;
• and
• third means connected to said second means and said adjusting means for providing a normalized exponent by modifying the exponent part provided from said adjusting means by an amount corresponding to said shift amount to normalize the exponent part of the operational result of the data pair;
• whereby said shifting means and said third means provide respectively a normalized mantissa part and a normalized exponent part ot either the operational result of the first pair of data or a floating point data corresponding to the fixed point data.

An arithmetic logic unit for floating point data and fixed point data, comprising:

• input means for selectively providing either a first pair of first and a second floating point data or second pair of first and second fixed point data;
• comparing means connected to said input means for comparing exponent parts of the pair of data to provide a comparison signal which shows which of the exponent parts is larger and to provide a difference signal indicating the difference therebetween;
• first shifting means connected to said input means and said comparing means for shifting a mantissa part on one of the pair data selected by the comparison signal by a first shift amount depending on the value of said difference signal;
• first prohibiting means connected to said first shifting means for prohibiting the shifting operation of said first shifting means in response to a first signal;
• selecting means connected to said input means and said comparing means for selecting an exponent part on the other of the pair data in response to said comparison signal;
• adding means connected to said shifting means and said input means for adding the shifted mantissa part and the mantissa part on the other of the data pair;
• second shifting means connected to said adding means for shifting an output of the adding means;
• detecting means connected to said adding means for detecting a second shift amount which is necessary for normalization of the output of the adding means, depending on the output of the adding means to control said second shifting means;
• second prohibiting means connected to said second shifting means for prohibiting shifting operation of said second shifting means in response to a second signal;
• modifying means connected to said selecting means for modifying the selected exponent part by an amount depending upon said second shift amount to normalize the selected exponent data;
• and
• control means for providing said first and second signals to said first and second prohibiting means, respectively, when said input means provides said second pair of first and second fixed point data.

An arithmetic logic unit for floating point data and fixed point data, comprising:

• a data storage for storing data including reference data;
• first means for selectively providing a first pair of first and second floating point data which are to be subjected to an arithmetic operation, or a second pair consisting of third floating point data which is to be converted to fixed point data and a fourth floating point data which is a reference data for the conversion and is delivered from the data storage when an instruction for the conversion is executed;
• and
• second means coupled to said first means for performing the arithmetic operation of said first pair of data and for performing normalization of said third floating point data with reference to an exponent part of said reference data.

An arithmetic logic unit for floating point data and fixed point data, comprising:

• input means for selectively providing either a first pair of first and second floating point data or a second pair of first and second fixed point data;
• adjusting means coupled to said input means for adjusting the first and second data of a selected pair to provide for each data of the selected pair an exponent part having the same value and two adjusted mantissa parts;
• adding means coupled to said adjusting means for adding the adjusted mantissa parts;
• normalizing means coupled to said adding means and said adjusting means for normalizing an output of said adding means and the adjusted exponent part;
• and
• control means coupled to said adjusting means and said normalizing means for providing a control signal which prohibits their operators when said input means provides said second pair of first and second fixed point data.