Method for successive approximation A/D conversion
AssigneeHarris Corporation
InventorsFrank R. Cooper, Kanti Bacrania
Life of this patent
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Abstract
A method of successive approximation A/D conversion employing an N bit internal D/A converter and an N bit SAR is provided wherein the first X bits are approximated to within less than the desired accuracy for N bit successive approximation while the last Y bits are approximated to within at least the desired accuracy for N bit successive approximation. After the Xth bit approximation, the A/D converter may be allowed sufficient time to settle to within the desired accuracy for N bit approximation during an error correction stage which increments or decrements the digital signal for the first X bits.
Claims10
A method of high speed digitizing of analog input signals to N bit digital numbers in a successive approximation analog to digital converter means having an internal digital to analog converter means and successive approximation register means both scaled for N bits comprising:
- a. supplying input signals to be digitized;
- b. successively approximating the states of the first X bits, where X is less than N and greater than one, at a rate which provides less than the desired accuracy of conversion for the first X bits of N bits of successive approximation conversion, but which provides at least the desired accuracy of conversion for the last Y bits, where Y plus X equals N;
- c. allowing the input signal to settle to at least the desired accuracy for N bits of successive approximation after successively approximating the Xth bit;
- d. comparing the input signal to a signal which is representative of said first X bits and digitally incrementing or decrementing at least one of said X bits in response to said comparison to correct for conversion inaccuracies;
- and
- e. successively approximating the states of the last Y bits, at said rate which provides at least the desired accuracy of conversion for said last Y bits, to complete the digitizing process.
A successive approximation analog to digital converter means for high speed digitizing of analog input signals to N bit digital numbers comprising:
- input means for receiving analog input signals to be digitized;
- comparator means connected to said input means for receiving analog input signals and for providing output signals as a function of the difference between first and second signals applied thereto;
- N bits successive approximation register means connected to said comparator means for producing digital output signals successively approximating the states of N bits of said digital numbers as a function of said output signals from said comparator means;
- N bit digital to analog converter means, connected to said N bit successive approximation register means and said comparator means, for producing analog signals as a function of the states of said N bits;
- and
- X bit counter means connected between the first X bits of the N bit successive approximation register means and the first X bits of the N bit digital to analog converter means, where X is less than N and greater than one;
- wherein said N bit successive approximation register means includes means for successively approximating the states of the first X bits at a rate which provides less than the desired accuracy of conversion for the first X bits of N bits of successive approximation conversion, but which provides at least the desired accuracy of conversion for the last Y bits, where Y plus X equals N;
- means for allowing the input signal to settle to at least the desired accuracy for N bits of successive approximation after successively approximating the Xth bit;
- means for comparing the input signal to a signal which is representative of said first X bits and means for digitally incrementing or decrementing said X bit counter in response to said comparison to correct for conversion inaccuracies;
- and
- means for successively approximating the states of the last Y bits, at said rate which provides at least the desired accuracy of conversion for said last Y bits, to complete the digitizing process.
Dependencies are inferred from the claim text.