US 4,612,629 AGranted

Highly scalable dynamic RAM cell with self-signal amplification

OwnerEliyahou Harariinventor

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Abstract

A dynamic RAM memory cell comprises an MOS read transistor whose conductivity state is determined by the state of charge on a first electrode overlying the read transistor channel region. The first electrode is connected through a buried contact opening to a diffused region in the substrate. This diffusion serves as a junction isolated storage node. This storage node can be charged or discharged through an MOS write transistor. The first electrode is capacitively coupled to a field plate held at a field potential. A control gate formed in a second electrode controls conduction through the write transistor and also allows selective reading in an array of read transistors. Nondestructive read can be achieved together with transistor amplification of the charge stored on the first electrode. Reduction in memory array area is achieved by using the source diffusion of the read transistor also as a buried field plate and by using the drain diffusion of the read transistor of one memory cell also as the drain diffusion of the write transistor of an adjacent cell.

A memory cell comprising:

semiconductor material of first conductivity type, said semiconductor material having a surface;
first, second, third and fourth regions of a second and opposite conductivity type formed in said semiconductor material adjacent to said surface, said first and second regions being separated by a first zone of said semiconductor material, said second and third regions being separated by a second zone of said semiconductor material, said third and fourth regions being separated by a third zone of said semiconductor material;
a first insulation layer formed on said semiconductor material;
a contact opening formed through said first insulation layer to said third region;
a first electrode attached to said third region through said contact opening in said first insulation layer, said first electrode being electrically isolated from said first, second and fourth regions, said first electrode extending on said first insulation layer over said second zone, over said second region and over at least part of said first zone, said first insulation layer being formed between said first electrode and said semiconductor material;
a second insulation layer formed to cover said first electrode;
a second electrode formed on said second insulation layer over said first electrode, said second electrode also extending on a third insulation layer over said third zone to said fourth region, said second electrode forming a word line, said first electrode and said word line forming a dual electrode structure, said dual electrode structure forming a read transistor with channel length measured by the extent of said first zone between said first and second regions and channel width measured by the extent of not more than the width of said first electrode, said dual electrode structure also forming a write transistor with a channel whose length is measured by the extent of said third zone between said third and fourth regions and whose width is measured by the extent of not more than the width of said word line;
an isolation region formed in said second zone;
a field isolation region surrounding said read and write transistors;
and
a storage junction formed between said third region and said semiconductor material of said first conductivity type.

8 more elements

Facts

Application

06/537,477Filed 30 Sep 1983 · continuation in part

Priority

13 Jul 1981

Granted

16 Sep 1986

Term ends

Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10B 69/00
Erasable-and-programmable rom [eprom] devices not provided for in groups h10b41/00 - h10b63/00
G11C 11/405
With charge regeneration common to a multiplicity of memory cells, i.e. external refresh: with three charge-transfer gates, e.g. MOS transistors,…
G11C 11/4125
Using field-effect transistors only: cells incorporating circuit means for protecting against loss of information
G11C 11/565
Using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency: using capacitive charge…

Family

Serial282,882Parent of this continuation-in-part · filed 13 Jul 1981

Serial355,986Parent of this continuation-in-part · filed 8 Mar 1982

US 4,448,400 AParent of this continuation-in-part

US 4,417,325 AParent of this continuation-in-part

US 4,612,629 AThis patent

From the US filing history. Foreign family members aren’t listed.

Abstract

Claims46