Burst-to-line-locked clock digital video signal sample rate conversion apparatus
AssigneeRCA Corporation
InventorsWillem den Hollander, Werner N. Hartmeier
Life of this patent
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Abstract
A digital video signal processing system is described wherein analog video signal is sampled by a sampling clock phase locked to burst and the digital video samples are processed with a clock phase locked to horizontal sync. The respective sampling phases of the sampling clock are encoded and concatenated with the digital video samples for purposes of synchronously demodulating the color difference signals of composite video. Burst clock to line locked clock sample conversion is accomplished in a FIFO memory.
Claims12
A video signal processing system for processing composite video signal including a burst reference component and a horizontal synchronizing component, comprising:
- means responsive to said burst reference component for developing a sampling clock signal phase locked thereto;
- a sampling clock phase encoder, responsive to said means for developing the sampling clock signal, for developing codes designating respective sampling phases of said sampling clock signal;
- a source of digital video samples, said digital video samples having predetermined phase relationships with said sampling clock;
- means responsive to said horizontal synchronizing component for developing a line locked clock phaselocked to said horizontal synchronizing component and having a frequency substantially equal to the frequency of said sampling clock signal;
- memory means responsive to said sampling clock signal for storing said digital video samples and associated sampling clock phase codes, and responsive to said line locked clock for outputting said digital representations and associated sampling clock phase codes asynchronously with said sampling clock;
- and
- utilization means coupled to said memory means for processing said digital video samples and responsive to said sample clock phase codes for maintaining a phase coherence between said samples and said line locked clock.
A video signal processing system for processing composite video signal including a color component, said video signal in sampled data format and sampled synchronously with said color component at regularly recurring phases of said color component, comprising:
- a source of sample clock signal which is synchronous with said video signal samples;
- means coupled to said source of sample clock signal for providing sample clock digital codes corresponding to respective sampling phases of said video samples;
- a source of processing clock signal having a frequency substantially equal to the frequency of said sample clock signal and asynchronous therewith;
- memory means having an input port for applying said sample data video signal and said sample clock digital codes, for storing said video signal and respective associated digital codes synchronously with said sample clock signal, and for reading said stored video signal and associated digital codes synchronously with said processing clock signal, wherein said storing and reading operations occur concurrently.
A video processing system for processing a composite video signal including a burst reference component and a horizontal synchronizing component, comprising:
- means responsive to said burst reference component for developing a sampling clock signal phase locked thereto;
- an analog-to-digital converter responsive to said sampling clock signal for developing digital representations of said composite video signal;
- means responsive to said horizontal synchronizing component for developing a processing clock signal phase locked thereto and having a frequency substantially equal to said sampling clock signal;
- memory means coupled to said analog-to-digital converter and said sampling clock signal for sequentially storing said digital representations synchronously with said sampling clock signal, and responsive to said processing clock signal for sequentially reading said digital representations from memory synchronously with said processing clock signal, wherein storing into and reading from memory occur concurrently;
- and
- means for advancing the read sample sequence by two samples for each field of composite video signal.
Dependencies are inferred from the claim text.