Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making

An improved solder interconnection for forming I/O connections between an integrated semiconductor device and a support substrate comprising

• a plurality of solder connections arranged in an area array joining a set of I/O's on a flat surface of said semiconductor device to a corresponding set of solder wettable pads on a substrate,
• a band of dielectric organic material disposed between and bonded to said device and substrate embedding at least an outer row of solder connections, and leaving the central inner solder connections and the central underside device surface and opposing substrate surface and also the top surface of the device being free of said dielectric organic material.