Programmable controller

A programmable controller, comprising:

• an arithmetic control unit for executing logic operations with input signals to provide output signals, and for generating address signals;
• a unit bus for transmitting said input and output signals;
• an address bus for transmitting said address signals, wherein said address bus transmits a clock signal;
• and
• a plurality of external units connected to said arithmetic control unit by said unit bus and said address bus for executing at least one of the operations of receiving input signals to be transmitted through said unit bus to said arithmetic control unit and sending of said output signals of said arithmetic control unit through said unit bus to drive an external load on the basis of commands of said arithmetic control unit, each of said external units including a selection latch circuit having a clock terminal connected to said address bus to receive said clock signal, said selection latch circuits being connected in series by said address bus to the corresponding latch circuit of succeeding of said units whereby said clock signal supplied to said external units may be transmitted to said selection latch circuits of succeeding-stage units, said selection latch circuits rendering one of the corresponding external units conductive with said unit bus when latching said address signal sent from said arithmetic control unit through said address bus, said selection latch circuits being connected to the respective external units by said address bus whereby said address signal supplied to said external units may be transmitted to said selection latch circuits of succeeding-stage units.

A programmable controller comprising:

• an arithmetic control unit for executing logic operations with input signals to provide output signals, and for generating address signals;
• a unit bus for transmitting said input and output signals;
• an address bus for transmitting said address signals;
• an input unit connected to said arithmetic control unit by said unit bus and address bus for receiving said input signals to be transmitted through said unit bus to said arithmetic control unit, on the basis of commands of said arithmetic control unit and having a selection latch circuit appointing the corresponding input units responsive to said unit bus when latching said address signals;
• and
• an output unit connected to said arithmetic control unit by said unit bus and address bus for sending said output signals of said arithmetic control unit through said unit bus on the basis of commands of said arithmetic control unit, and having a selection latch circuit appointing the corresponding output unit responsive to said unit bus when latching said address signal;
• said selection latch circuits being connected to the respective units by said address bus whereby said address signal supplied to said external units may be transmitted to said selection latch circuits of succeeding-stage units.

A programmable controller comprising:

• an arithmetic control unit for executing logic operations with input signals to provide output signals, and for generating address signals;
• a unit bus for transmitting said input and output signals;
• an address bus for transmitting said address signals;
• an input unit connected to said arithmetic control unit by said unit bus and address bus for receiving said input signals to be transmitted through said unit bus to said arithmetic control unit on the basis of commands of said arithmetic control unit having a multi-bit input buffer for transmitting said input signals to said arithmetic control unit through said unit bus, and having a multi-bit selection latch circuit for rendering the corresponding input buffer responsive to said unit bus while shifting said address signals;
• and
• an output unit connected to said arithmetic control unit by said unit bus and address bus for sending said output signals of said arithmetic control unit through said unit bus on command of said arithmetic control unit, and having a multi-bit output latch circuit for receiving and sending said output signals to an external load, and having a multi-bit selection latch circuit conductively connecting the corresponding output latch circuit of a corresponding output unit to said unit bus and said external load;
• said each selection latch circuit of each input and output units being connected in series in a clock line by said address bus to the corresponding latch circuit of succeeding ones of said units, whereby each bit of said selection latch circuits is connected in series to transmit said clock signal to succeeding-stage bits and designate each bit of said input buffer and output latch circuit to be selected in order of timesharing.