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US 4,602,168 AGranted
Low offset CMOS comparator circuit
AssigneeNational Semiconductor Corporation
InventorPeter S. Single
Life of this patent
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Abstract
A CMOS comparator circuit is disclosed in which a low offset is achieved without trimming. The input stage is composed of a pair of bipolar transistors which have lateral non-dedicated collectors that operate in parallel with the substrate dedicated collectors. The input stage includes matched load devices and is followed by an amplifier having a differential to single ended converter.
Claims4
A CMOS comparator circuit having a single ended output terminal and first and second differential input terminals, said circuit comprising:
- an input stage comprising a pair of bipolar transistors, each one having an emitter, a base, a substrate dedicated collector, and a lateral collector adjacent to said emitter;
- means for coupling said input stage transistor bases to said comparator input terminals;
- means for coupling said pair of bipolar transistor emitters together and to a constant current sink to provide differential operation;
- matched transistor load means coupled to said lateral collectors of said pair of bipolar transistors;
- and
- amplifier means for coupling said matched transistor load means to said comparator output terminal.
3 more elements
Dependencies are inferred from the claim text.