Repairable ROM array

A memory circuit comprising a Read Only Memory (ROM) having a plurality of memory locations, which contain data bits, arranged in rows and columns to define a ROM array, wherein the data bit in one selected memory location in each column is a check bit which has been derived from the intended contents of the respective column, the memory circuit further comprising means for accessing selected rows in the ROM array in response to the receipt of the address of each selected row, and apparatus for repairing the ROM array by replacing a row which has been found to have one or more defects, said repairing apparatus comprising means for storing the address of the defective row, a spare row of programmable memory for storing the data bits intended to have been stored in the defective row, means for comparing the incoming row address with the stored address of the defective row and for generating a spare select signal whenever said incoming new address and said stored address coincide, said spare select signal being arranged to disable said means for accessing selected rows and to enable access to said spare row whereby said defective row is replaced by said spare row, wherein said apparatus further comprises writing means arranged when enabled to write data into said spare memory row, the data written into the spare row having been generated from the data and check bits actually contained in the whole of the ROM array except for the defective row.

A method of repairing a Read Only Memory (ROM) having a plurality of memory locations which contain data bits, arranged in rows and columns to define a ROM array, the method comprising the steps of:

• storing in the ROM a set of check bits derived from the data intended to be stored in said ROM, each column having a corresponding check bit;
• testing the ROM to identify a defective row therein;
• storing the address of a defective row;
• generating data from data and check bits stored in the ROM array, excluding said defective row, and storing the generated data in a spare row of programmable memory, said generation step being such that the generated data corresponds to the data intended to have been stored in the defective row;
• and
• accessing said spare row whenever said defective row is addressed such that said defective row is replaced by said spare row.