Scanning sample, signal generation, data digitizing and retiming system

A data stream speed-reduction and duty-cycle-improvement system comprising:

• a first random access memory having address inputs;
• a data input and a data output;
• a first binary counter, in the first mode counting timing signals and in the second mode counting clock pulses, having outputs connected to the address inputs of the first random access memory;
• a second random access memory having address inputs;
• a data input and a data output;
• a second binary counter, in the first mode counting clock signals and in the second mode counting timing signals, having outputs connected to the address inputs of the second random access memory;
• means for generating timing signals at the first, higher frequency;
• clock means for generating clock signals at the second, lower frequency;
• a bistable circuit, stable in either a "1" state or a "0" state, having facility for changing state when alternation is required;
• a first plurality of steering gates, enabled when the bistable circuit is in the "1" state for conveying timing signals from the timing signal generating means to the first counter and clock signals from the clock signal generating means to the second counter;
• and
• a second plurality of steering gates, enabled when the bistable circuit is in the "0" state for conveying timing signals from the timing signal generating means to the second counter and clock signals from the clock signal generating means to the first counter.

A data stream speed-reduction and duty-cycle-improvement system comprising:

• first memory means for selectively storing data of the data stream at a first, higher frequency and for reading said data out at a second, lower frequency;
• second memory means for selectively storing data of the data stream at a first, higher frequency and for reading said data out at a second, lower frequency;
• means for alternating between a first mode and a second mode, in the first mode for causing the first memory means to store data while causing the second memory means to read out data, in the second mode for causing the second memory means to store data while causing the first memory means to read out data;
• means for generating timing signals at the first, higher frequency;
• clock means for generating clock signals at the second, lower frequency;
• and
• means responsive to the clock signal generating means for controlling the frequency of the timing signals generated by the timing signal generating means.

A system according to claim 16 wherein the controlling means comprises:

• means responsive to the output of the clock signal generating means for generating drive signals at a frequency that is a fraction of the frequency of the clock signals;
• a synchronous motor driven by the drive signal generating means at a speed which is in synchronism with the clock signals;
• a source of focused energy;
• means driven by the motor for modulating the focused energy in synchronism with the clock signals;
• and
• means for sensing the modulated energy and for controlling the operation of the timing signal generating means in response to the frequency at which the focused energy is modulated.

A system according to claim 17 wherein the modulating means comprises:

• a drum connected for rotation with the motor, the drum being positioned to intercept at its periphery, the focused energy;
• a plurality of mirrors on the periphery of the drum, positioned to reflect the focused energy, whereby rotation of the mirrored drum sweeps the reflected, focused energy in a path;
• and
• means located in the path swept by the focused energy for alternately blocking and passing the focused energy to the sensing means.

A data stream speed-reduction and duty-cycle improvement system comprising:

• a first memory for receiving, storing, and transmitting data seriatim;
• a second memory for receiving, storing, and transmitting data seriatim;
• means for generating timing signals having a frequency corresponding to the rate at which data are received by the memories;
• means for generating clock signals having a frequency corresponding to the rate at which data are transmitted by the memories;
• routing means for controlling the routing of the timing signals alternately to the first and second memories and of the clock signals alternately to the second and first memories;
• means responsive to the first plurality of a group of timing signals for causing the routing means to reverse the routing of the timing signals and the clock signals;
• and
• means responsive to the clock signals for controlling the frequency of the means for generating the timing signals.