US 4,598,460 AGranted

Method of making a CMOS EPROM with independently selectable thresholds

AssigneeSolid State Scientific Corporation

InventorsAlexander H. Owens, Mark A. Halfacre, David S. Pan

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Abstract

A process for making an integrated cirucit EPROM having an array of EPROM devices and CMOS peripheral circuits, including blanket depositions of a first and a second polysilicon layers on a silicon substrate and removing portions of those polysilicon layers. The EPROM floating gate is made from the first polysilicon layer, and the EPROM control gate as well as the P-channel and N-channel gates of the peripheral transistors are all made from the second polysilicon layer. Independently adjustable thresholds for each of the three device types are made possible by forming an N-well at the substrate region at which the P-channel device is to be built, blanket implanting all three channels prior to selectively forming the first polysilicon layer over the EPROM region, and then selectively doping the channels of the N- and P-channel devices only.

Claims10

Dependent claims

A method of fabricating on a P-conductivity type substrate an N-channel EPROM FET having self-aligned floating and control gates, a separate N-channel FET device, and a separate P-channel FET device in an N-conductivity type well region formed in said substrate comprising the steps of:

(a) masking said substrate to cover the substrate regions at which said EPROM FET and N-channel device are to be formed and introducing N-type impurities into said substrate to form an N-well region at a portion thereof at which said P-channel device is to be formed;
(b) simultaneously introducing P-type impurities into the channel regions of said EPROM FET, said P-channel and said N-channel devices;
(c) selectively forming a first polysilicon layer over the region of the substrate at which said EPROM device is to be formed;
(d) selectively introducing P-type impurities in said channel regions of said P-channel and N-channel devices while said EPROM region is covered by said first polysilicon layer;
(e) forming a second polysilicon layer over the substrate region wherein said EPROM, said P-channel and said N-channel devices are to be formed;
(f) forming on said second polysilicon layer a masking layer just over a central portion of said EPROM region and entirely over said P-channel and N-channel device regions;
(g) removing the portions of said first and second polysilicon layers not covered by said masking layer thereby shaping the EPROM self-aligned floating and control gates;
(h) subsequently etching away portions of said second polysilicon layer to form the gates of the P- and N-channel devices;
and
(i) introducing impurities at selected regions of said substrate to form the sources and drains of each of the devices.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 06/680,197Filed 10 Dec 1984
Granted: 8 Jul 1986
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10B 41/40
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the peripheral circuit region
H10B 41/49
Simultaneous manufacture of periphery and memory cells: comprising different types of peripheral transistor
H10D 84/0165
The components including insulated gates, e.g. IGFETs: the components including complementary IGFETs, e.g. CMOS devices
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe