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US 4,598,390 AGranted
Random access memory RAM employing complementary transistor switch (CTS) memory cells
AssigneeInternational Business Machines Corporation
InventorYuen H. Chan
Life of this patent
Estimating the term…
Abstract
The disclosure is directed to an improved random access memory (RAM). More particularly to improved bit selection circuitry for use in an array preferably employing unclamped CTS (Complementary Transistor Switch) type memory cells.
Claims23
In a monolithic random access memory for storing binary data, said memory comprising:
- an array of memory cells having m columns and n rows, where m and n are positive integers, and said memory array including m.times.n memory cells, where each of said cells has the capacity to store one binary bit and each of said n rows of memory cells has the capacity to store m binary bits;
- m pairs of bit lines each pair of said m pairs of bit lines including a first bit line BL and a second bit line BR;
- n pairs of word lines each pair of said n pairs of word lines including an upper (word) word line and a lower (drain) word line;
- each of said memory cells of said m.times.n array of memory cells being connected to the first bit line BL and the second line BR of a predetermined one of said m pairs of bit lines;
- each of said memory cells of said m.times.n array of memory cells being also connected to the upper (word) word line and the lower (drain) word line of a predetermined one of said n pairs of word lines;
- m bit select circuits, each of said m bit select circuits being connected to a discrete one of said m pairs of bit lines;
- a switchable bit up level clamp circuit having an output terminal connected to each of said m bit select circuits;
- bit address decoder circuit means coupled to said m bit select circuits for selecting at least one of said bit select circuits;
- word line decoder circuit means coupled to said n pairs of word lines for selecting one of said n pairs of word lines, whereby the operation of said bit address decoder circuit means in conjunction with the operation of said word line decoder circuit means effects the selection of at least a predetermined one of said m.times.n array of memory cells;
- and
- each of said m bit select circuits including,
- first, second, third, fourth, fifth and sixth transistors, said first, second, third and fourth transistors each having an emitter base and collector, said fifth and sixth transistors each having first and second emitters, a base and a collector, said emitter of said first transistor and said base of said third transistor being connected in common, said emitter of said second transistor and said base of said fourth transistor being connected in common, said collector of said third transistor and said collector of said fourth transistor being connected in common to a first source of potential,
- a first resistor connected between a common connection of said base of said first transistor, said collector of said fifth transistor and said base of said fifth transistor, and said first source of potential,
- a second resistor connected between a common connection of said base of said second transistor, said collector of said sixth transistor and said base of said sixth transistor, and said first source of potential,
- a third resistor (RBL) connected across the base-emitter junction of said third transistor,
- a fourth resistor (RBL) connected across the base-emitter junction of said fourth transistor,
- a first Schottky diode connected between the emitter of said third transistor and the collector of said first transistor,
- a second Schottky diode connected between the emitter of said fourth transistor and the collector of said second transistor,
- said first bit line (BL) of said one of said m pairs of bit lines being connected to said emitter of said third transistor,
- said second bit line (BR) of said one of said m pairs of bit lines being connected to said emitter of said fourth transistor,
- a common connection between said collectors of said first and second transistors and said bit address decoder circuit means,
- a common connection between said second emitters of said fifth and sixth transistors and said switchable bit up level clamp circuit output terminal, and
- said first emitters of said fifth and sixth transistors being respectively connected to a WRITE control circuit.
20 more elements
In a monolithic random access memory for storing binary data, said memory comprising:
- an array of memory cells having m columns and n rows, where m and n are positive integers, and said memory array including m.times.n memory cells, where each of said cells has the capacity to store one binary bit and each of said n rows of memory cells has the capacity to store m binary bits;
- m pairs of bit lines, each pair of said m pairs of bit lines including a first bit line BL and a second bit line BR;
- n pairs of word lines, each pair of said n pairs of word lines including an upper (word) word line WL and a lower (drain) word line DL;
- each of said memory cells of said m.times.n array of memory cells being connected to the first bit line BL and the second bit line BR of a predetermined one of said m pairs of bit lines;
- each of said memory cells of said m.times.n array of memory cells being also connected to the upper (word) word line and the lower (drain) word line of a predetermined one of said n pairs of word lines;
- m bit select circuits, each of said m bit select circuits being connected to a discrete one of said m pairs of bit lines;
- a switchable bit up-level clamp circuit, said switchable bit up-level clamp circuit having an output terminal connected to each of said m bit select circuits;
- bit address decoder circuit means, said bit address decoder circuit means having a plurality of select lines coupled to said m bit select circuits for selecting at least one of said bit select circuits;
- and
- word line decoder circuit means, said word line decoder circuit means coupled to said n pairs of word lines for selecting one of said n pairs of word lines, said word line decoder having a first level of circuitry for receiving a word address and a second level of circuitry connecting said first level of circuitry to said n pair of word lines, whereby the operation of said bit address decoder circuit means in conjunctions with the operation of said word line decoder circuit means effects the selection of at least a predetermined one of said m.times.n array of memory cells;
- and,
- each of said m bit select circuits including,
- first, second, third, fourth, fifth and sixth transistors, said first, second, third and fourth transistors each having an emitter base and collector, said fifth and sixth transistors each having first and second emitters, a base and a collector, said emitter of said first transistor and said base of said third transistor being connected in common, said emitter of said second transistor and said base of said fourth transistor being connected in common,
- a first resistor connected between a common connection of said base of said first transistor, said collector of said fifth transistor and said base of said fifth transistor, and a first source of potential,
- a second resistor connected between a common connection of said base of said second transistor, said collector of said sixth transistor and said base of said sixth transistor, and said first source of potential,
- a third resistor (RBL) connected across the base-emitter junction of said third transistor,
- a fourth resistor (RBR) connected across the base-emitter junction of said fourth transistor,
- a first Schottky diode connected between the emitter of said third transistor and the collector of said first transistor,
- a second Schottky diode connected between the emitter of said fourth transistor and the collector of said second transistor,
- said first bit line (BL) of said one of said m pairs of bit lines being connected to said emitter of said third transistor,
- said second bit line (BR) of said one of said m pairs of bit lines being connected to said emitter of said fourth transistor,
- a common connection between said collectors of said first and second transistors and said bit address decoder circuit means,
- a common connection between said second emitters of said fifth and sixth transistors and said switchable bit up level clamp circuit output terminal, and
- said first emitters of said fifth and sixth transistors being respectively connected to a WRITE control circuit.
21 more elements
In a monolithic random access memory for storing binary data, as recited in 10, wherein each of said n outputs of said decoder circuit is a push-pull transistor pair including an emitter follower transistor whose emitter is coupled to the upper (word) word line of the predetermined one of said n pairs of word lines and said push-pull transistor pair further including an open collector transistor whose collector is coupled to the lower (drain) word line of the predetermined one of said n pairs of word lines.
Dependencies are inferred from the claim text.