US 4,597,084 A · Computer memory apparatus

Abstract

A fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units.

Claims17

Dependent claims

In random-access computer memory apparatus for reading and for writing digital information transferred to and from other computer apparatus by way of a bus structure having at least first and second duplicative buses, the improvement comprising

A. first and second independently operable random access memory means, each of which is arranged for storing portions of memory words, and which together are arranged for storing complete memory words,
B. first means for applying to each one of said memory means a different memory word portion received from either of said first and second buses,
C. second means for applying to each of said first and second buses a memory word portion read from one said memory means,
D. error checking means connected with said second means for responding to an invalid memory word portion to produce a fault-reporting signal,
E. parity generating means connected with said first means for appending at least one parity digit to each memory word portion and for appending further parity information to each complete memory word being written in said memory means, and
F. error correcting means connected with said second means for responding to said fault-reporting signal and to said parity digits and to said parity information for correcting at least single-bit errors in a memory-read word.

3 more elements

In random-access computer memory apparatus for reading and for writing digital information transferred to and from computer central processing apparatus by way of a bus structure having at least first and second duplicative buses, the improvement comprising

A. first and second independently operable random access memory means, each of which is arranged for storing portions of memory words and which together are arranged for storing complete memory words,
B. multiplexor means for applying to each of said memory means different word portions received from any one of said first and second buses,
C. output means for applying each memory word portion read from said memory means to both of said first and second buses,
D. code checking means connected with said output means for responding to an invalid memory word coding to produce a fault-reporting signal,
E. first code-introducing means connected with said multiplexor means and with said memory means for appending a selected digital code in each word portion applied to each said memory means, and
F. second code-introducing means connected with said multiplexor means and with said memory means for appending a selected digital code in each two-portion word applied to said two memory means.

3 more elements

A. first and second independently operable random access memory means, each of which is arranged for storing portions of memory words and which together are arranged for storing complete memory words,
B. multiplexor means for applying to each of said memory means different word portions received from any one of said first and second buses,
C. output means for applying each memory word portion read from said memory means to both of said first and second buses,
D. code checking means connected with said output means for responding to an invalid memory word to produce a fault-reporting signal,
E. first and second parity introducing means for appending a selected parity condition in each word portion applied to said first and second memory means, and
F. code introducing means for appending a selected error checking and correcting code in each two-portion word applied to said two memory means.

3 more elements

A. first and second independently operable random access memory means each of which has a plurality of addressable storage locations for storing memory word portions,
B.memory write means for applying a selected addressable location of said first memory means and to a selected addressable location of said second memory means portions of a complete memory word received from at least one of said first and second buses, said memory word portions being applied to said memory means for together forming a complete memory word,
C. memory read means for applying to each of said first and second buses a memory word portion read from a selected addressable location of at least one of said first and second memory means,
D. error checking means connected with said memory read means for detecting an error caused by the invalid addressing of an addressable location of at least one of said memory means by at least one of said memory read means and said memory write means, said error checking means including means for producing a fault-reporting signal in response to said detected error,
E. first and second parity introducing means for appending a selected parity condition in each word portion applied to said first and second memory means, and
F. code introducing means for appending a selected error checking and correcting code in each two-portion word applied to said two memory means.

3 more elements

Dependencies are inferred from the claim text.

Computer memory apparatus

Life of this patent

Computer memory apparatus

Life of this patent

Abstract

Claims17