US 4,594,655 AGranted

(k)-Instructions-at-a-time pipelined processor for parallel execution of inherently sequential instructions

AssigneeInternational Business Machines Corporation

InventorsHsieh T. Hao, Huei Ling, Howard E. Sachar, Jeffrey Weiss, Yannis J. Yamour

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Abstract

Equipping a secondary data flow facility with additional capability, to emulate for certain operations the simultaneous processing of the prerequisite instruction and the dependent instruction, significantly improves simultaneous pipeline processing of inherently sequential instructions (k)-at-a-time, by eliminating delays for calculating prerequisite operands. For example, Instruction A+B=Z1 followed by Instruction Z1+C=Z2 is inherently sequential, with A+B=Z1 the prerequisite instruction and Z1+C=Z2 the dependent instruction. The specially equipped secondary data flow facility does not wait for Z1, the apparent input operand from the prerequisite instruction; it simulates Z1 instead, performing A+B+C=Z2 in parallel with A+B=Z1. All data flow facilities need not be fully equipped for all instructions; the secondary data flow facility may be generally less massive than a primary data flow facility, but is more sophisticated in a critical organ, such as the adder. The three-input adder of the secondary data flow facility emulates the result of a two-input adder of a primary data flow facility, occuring simultaneously in the two-input primary data flow facility adder, adding the third operand to the emulated result, without delay. The instruction unit decodes the instruction sequence normally to control (k)-at-a-time execution where there are no instruction interlocks or dependencies; to delay execution of dependent instructions until operands become available; and to reinstate (k)-at-a-time execution in a limited number of cases by using the additional capability of the secondary data flow facility to emulate the prerequisite operands. A control unit performs housekeeping to execute the instructions.

Claims4

Dependent claims

A pipelined processor comprising

(a) a pipeline instruction control unit;
(b) at least one primary data flow facility having a plurality of inputs and having a subassembly processing a finite number (n) of said inputs in parallel, to process a stream of instructions defined by the instruction control unit;
(c) one or more secondary data flow facilities having a plurality of inputs and each said data flow facility having a subassembly processing a greater number (n)+(k-1)(n-1) of said inputs than the finite number of inputs being processed by said primary data flow facility, said secondary data flow facility comprising at least one comparable subassembly similar in function to said subassembly in said primary data flow facility but with a greater number of inputs, whereby said secondary data flow facility can process all the inputs required to emulate the apparent result of processing by said comparable subassembly of the primary data flow facility and process said apparent result together with an additional input;
(d) an instruction unit comprising means to detect adjacent instruction groups including:
interlocked instruction sequences where on adjacent instruction necessarily must be delayed pending completion of another;
adjacent instruction sequences in which one of a group of adjacent instructions requires operand inputs including an operand input which is the result of processing the operand inputs for another instruction of the group;
and
independent adjacent instruction sequences which require unrelated operand inputs;
(e) control means connected to said instruction unit and said primary and secondary data flow facilities to control simultaneous processing of dependent adjacent instruction sequences and independent adjacent instruction sequences, and to delay processing of appropriate instructions when necessary in interlocked instruction sequences;
wherein said primary data flow facility is a minimum data flow facility equipped to process inputs, and said one or more secondary data flow facilities, in sequence by complexity, are equipped to process (n)+(k-1)(n-1) inputs, where (n) is the number of inputs to said minimum facility, (n) being an integer equal to or greater than 1, and (k) is the facility sequence position number.

7 more elements

A pipelined processing comprising:

(a) a pipeline instruction control unit,
(b) a primary data flow facility having inputs and having a reference capability to process a stream of instructions defined by said instruction control unit, said primary data flow facility comprising an (n)-input adder to produce for a given instruction a result;
(c) a secondary data flow facility having inputs and capability different from said reference capability of the primary data flow facility, comprising a (2n-1)-input adder so that the secondary data flow (2n-1)-input adder can process said inputs to said primary data flow facility n-input adder to emulate said result of processing by said (n)-input adder of said primary data flow facility as a subset of its input set;
(d) an instruction unit comprising means to detect adjacent instruction groups including:
interlocked instruction sequences where one adjacent instruction necessarily must be delayed pending completion of another;
adjacent instruction sequences in which one of a group of adjacent instructions require operand inputs including an operand input which is the result of processing the operand inputs for another instruction of the group;
and
independent adjacent instruction sequences which require unrelated operand inputs;
and
(e) control means connected to said instruction unit and said primary and secondary data flow facilities to control simultaneous processing of dependent adjacent instruction sequences and independent adjacent instruction sequences, and to delay processing of appropriate instructions when necessary in interlock instruction sequences.

7 more elements

Dependencies are inferred from the claim text.