Method for making vertical channel field controlled device employing a recessed gate structure

A method of fabricating a vertical channel junction gate electric field controlled device having a recessed gate structure and being of the type including a semiconductor base region of one conductivity type and a gate region of opposite conductivity type, said method comprising:

• providing a semiconductor wafer having a base layer of the one conductivity type and of crystallographic orientation selected to facilitate preferential etching and the formation of substantially vertical-walled gate grooves;
• forming at the upper surface of the base layer an upper electrode region layer of the one conductivity type but of higher conductivity than the base layer;
• forming a layer of silicon dioxide with a plurality of elongated windows on the upper surface of the upper electrode region, the windows defining the ultimate locations of the gate regions and the oxide layer portions between the windows defining the ultimate locations of upper electrode regions;
• preferentially etching the upper electrode region layer and the base layer to form substantially vertically-walled gate grooves below the windows;
• partially refilling the grooves with semiconductor material of the opposite conductivity type to provide a gate structure;
• removing the silicon dioxide layer to expose the upper electrode regions;
• and
• evaporating metal onto the the wafer surface to form metallized electrode terminals in ohmic contact with the upper electrode regions and elongated metallized gate terminal fingers in ohmic contact with the gate regions at the bottoms of the grooves.

A method of fabricating a vertical channel junction gate electric field controlled device having a recessed gate structure and being of the type including a semiconductor base region of one conductivity type and a gate region of opposite conductivity type, said method comprising:

• providing a semiconductor wafer having a base layer of the one conductivity type and of crystallographic orientation selected to facilitate preferential etching and the formation of substantially vertically walled gate grooves;
• forming at the upper surface of the base layer an upper electrode region layer of the one conductivity type but of higher conductivity than the base layer;
• forming a layer of silicon dioxide with a plurality of parallel elongated windows on the upper surface of the upper electrode region, alternate windows defining the ultimate locations of upper electrode region contacts and gate regions;
• forming an etchant barrier of silicon nitride patterned so as to cover the windows in the silicon dioxide layer defining the ultimate locations of upper electrode region contacts and to leave open the windows in the silicon dioxide layer defining the ultimate location of gate regions;
• preferentially etching the upper electrode region layer and the base layer to form substantially vertically-walled grooves beneath the gate region windows, with undercutting of the oxide layer surrounding the gate region windows;
• partially refilling the grooves with semiconductor material of the opposite conductivity type to provide a gate structure;
• removing the silicon nitride barrier to expose the windows in the silicon dioxide layer defining the ultimate locations of the upper electrode region contacts;
• and
• evaporating metal onto the wafer surface to form metallized electrode terminals in ohmic contact with the upper electrode regions, and to form elongated metallized gate terminal fingers in ohmic contact with the gate regions at the bottoms of the grooves.