MOS rear end processing
AssigneeIntel Corporation
InventorsLeopoldo D. Yau, Robert A. Gasser, Jr., Kenneth R. Week, Jr., Jick M. Yu, David D. Chin
Life of this patent
Estimating the term…
Abstract
A process for the reduction of defect formation in conductive layers of semiconductor bodies during patterning, alloying and passivation. A film of low temperature spin-on-glass containing dye is formed on the conductive layer prior to patterning and any high temperature process greater than 200 degrees C. Hermetic passivation is achieved by depositing on the conductive layer a composite film consisting of a lower, tensile layer and an upper, compressive layer with the net force of the passivation film being tensile.
Claims7
A process for forming a patterned, alloyed conductive layer on a semiconductor body comprising the steps of:
- a. depositing a metallic conductive layer over said semiconductor body;
- b. depositing a layer of low temperature spin-on-glass on said conductive layer;
- said spin-on-glass containing dye;
- and,
- c. any patterning of said conductive layer and heating cycle greater than 200 degrees C. done after said depositing of said low temperature spin on glass,
- whereby the formation of hillocks and voids in said conductive layer is inhibited, and said spin-on-glass acts as an antireflective coating during patterning.
A process for forming a patterned, alloyed conductive layer on a silicon substrate comprising the steps of:
- depositing a metallic conductive layer over said silicon substrate;
- forming a layer of spin-on glass on said conductive layer, said spin-on glass layer containing dye;
- patterning said conductive layer utilizing photolithographic techniques;
- heating said silicon substrate to a temperature sufficient to alloy said conductive layer and said silicon substrate.
Dependencies are inferred from the claim text.