Method for manufacturing a gate array integrated circuit device

A method for manufacturing a gate array integrated circuit device which comprises a logic system formed on a semiconductor substrate, comprising the steps of:

• (a) manufacturing basic cells in an array on the semiconductor substrate, each basic cell comprising a bulk pattern for an active electric element;
• (b) storing, in a memory, first symbol data and first detailed data corresponding to macro cells, each of which comprises one or more basic cells and wiring connecting the active electric elements of the basic cell, and each of which has a standard first logic function, the first symbol data identifying each of the macro cells, the first detailed data identifying the connection of the active electric elements of each basic cell and the standard first logic function for each or the macro cells;
• (c) storing, in the memory, second symbol data and second detailed data corresponding to expanded macro cells, each of which is an MSI macro cell comprising a plurality of the macro cells, a plurality of terminals for connection outside the expanded macro cell, and wiring connecting the macro cells and the terminals, and each of which has a standard second logic function, the second symbol data including second symbols for identifying the expanded macro cells, the second detailed data identifying the macro cells, the terminals, the connections of the macro cells and the terminals, and the standard second logic function for each of the expanded macro cells;
• (d) storing, in the memory, third symbol data and third detailed data corresponding to custom expanded macro cells, each custom expanded macro cell corresponding to a modification of one of the expanded macro cells, and comprising a plurality of the macro cells, a plurality of terminals for connection outside the custom expanded macro cell, and wiring connecting the macro cells and the terminals, the third symbol data including third symbols for identifying the custom expanded macro cells, the third symbols being modifications of the respective corresponding second symbols, the third detailed data identifying the macro cells included in the custom expanded macro cells, the terminals, and the connections of the macro cells and the terminals, the number of at least one of the macro cells, terminals or wiring for each custom expanded macro cell, being less than that for the corresponding expanded macro cell;
• (e) storing, in the memory, logic system data corresponding to the logic system, the logic system data identifying the macro cells, the expanded macro cells and the custom expanded macro cells, and the wiring connecting the macro cells, the expanded macro cells, and the custom expanded macro cells, the logic system data comprising the first, second and third symbol data corresponding to the identified macro cells, expanded macro cells, and custom expanded macro cells, and the connections of the identified macro cells, expanded macro cells, and custom expanded macro cells;
• and
• (f) forming a conductive wiring pattern for the semiconductor substrate by synthesizing the logic system data and the first, second and third detailed data.

A method for generating a wiring pattern for a gate array integrated circuit device with the aid of a computer, the gate array integrated circuit device comprising a logic system formed on a semiconductor substrate, the logic system including macro cells formed by basic cells and having standard logic functions, and expanded macro cells which are MSI macro cells formed by combinations of the macro cells and which have standard logic functions, the method comprising the steps of:

• (a) providing the computer with a data base, including first symbol data and first detailed data corresponding to the macro cells, and second symbol data and second detailed data corresponding to the expanded macro cells, the first symbol data identifying each of the macro cells, the second symbol data identifying each of the expanded macro cells, the first detailed data identifying the connection of the active electric elements of the basic cell and the standard logic function for each of the macro cells, the second detailed data identifying the connection of the macro cells and the standard logic function for each of the expanded macro cells;
• (b) inputting logic system data comprising symbol data selected from the first and second symbol data representing the macro cells and the expanded macro cells, respectively, the logic system data further comprising data defining the interconnection of the expanded macro cells and the macro cells;
• and
• (c) generating, with the aid of the computer, the wiring pattern for the gate array integrated circuit device corresponding to the logic system data in accordance with the data base.