Slotted diaphragm semiconductor device
AssigneeHoneywell Inc.
InventorRobert G. Johnson
Life of this patent
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AssigneeHoneywell Inc.
InventorRobert G. Johnson
Estimating the term…
A semiconductor body comprises (100) silicon having a (100) plane and a [110] direction. A depression is formed in a first surface of the semiconductor body which is substantially parallel to the (100) plane. A slotted diaphragm is located over the depression and comprises a layer of thin film material and a resistance film. The depression is bounded at the first surface by four perpendicular boundary edges either in line with or perpendicular to the [110] direction. The slotted diaphragm has first and second slots having a first end located at a maximum width of the depression as measured along the line oriented at substantially 45 degrees to the [110] direction. Each of the first and second slots has a second end located so that each of the first and second slots extends only a portion of the distance across the maximum width of the depression as measured along the line oriented at substantially 45 degrees to the [110] direction. The slot apparatus further comprises third, fourth, fifth and sixth slots oriented substantially in line with or substantially perpendicular to the [110] direction. There is one of the third, fourth, fifth and sixth slots located at the substantial center of each of the four boundary edges. Each of the third, fourth, fifth and sixth slots has a length sufficient to permit undercutting of the diaphragm when an anisotropic etch is placed on each of the six slots.
An integrated semiconductor device, comprising:
An integrated semiconductor device, comprising:
An integrated semiconductor device, comprising:
A flow sensor, comprising:
A method of fabricating a slotted diaphragm semiconductor device comprising a slotted diaphragm of thin film material substantially covering a depression etched into a first surface of a semiconductor body, the depression being bounded at the first surface by a substantially square configuration comprising four substantially perpendicular boundary edges, each of the four substantially perpendicular boundary edges being substantially in line with or substantially perpendicular to a [110] direction in the semiconductor body, the method comprising the steps of:
Dependencies are inferred from the claim text.