Monolithic autobiased resistor structure and application thereof to interface circuits

In an integrated circuit an autobiased resistor structure fabricated on a P type semiconductor substrate comprising:

• an N type epitaxial layer formed on said substrate;
• a P type isolation wall extending through said epitaxial layer to said substrate, said isolation wall forming first and second isolated N type epitaxial pockets on said substrate;
• first and second spaced apart N+ type regions contained in said first N type epitaxial pocket;
• a first P type region contained in said first N type epitaxial pocket, said first P type region positioned between and spaced from said first and second N+ type regions contained in said first N type epitaxial pocket;
• an N+ type pocket contained in said first P type region contained in said first N type epitaxial pocket;
• a third N+ type region contained in said second N type epitaxial pocket;
• a first P+ type region contained in said second N type epitaxial pocket;
• an electrode, said electrode spaced from and coextensive with at least a portion of said first N+ type region contained in said first N type epitaxial pocket;
• first connection means electrically connecting said P+ type isolation wall, said P type substrate and said electrode to a source of potential V.sub.cc ;
• second connection means electrically connecting in common said first and second spaced apart N+ type regions contained in said first N type epitaxial pocket and said third N+ type region contained in said second N type epitaxial pocket;
• first, second and third spaced apart contacts, said first, second and third spaced apart contacts, in the order recited, electrically contacting said first P+ region contained in said second N type epitaxial pocket;
• third connection means electrically connecting in common said N+ type pocket contained in said first P type region, said first P type region contained in said first N type epitaxial pocket, said first contact and a source of potential V.sub.in ;
• fourth connection means connecting said third contact to a source of potential V.sub.GND ;
• fifth connection means connecting said second contact to an output terminal V.sub.out, for providing an output voltage V.sub.out, where the magnitudes of V.sub.in, V.sub.out and V.sub.GND bear the following relationship one to another .vertline.V.sub.in .vertline.>.vertline.V.sub.out .vertline.>.vertline.V.sub.GND .vertline.;
• and,
• said first P+ region is a voltage divider resistor having first, second and third taps provided by said first, second and third contacts, and said resistor is electrically isolated from said substrate by diode/capacitor circuit means.

In an integrated circuit an autobiased resistor structure fabricated on a P type semiconductor substrate, as recited in claim 2, wherein the equivalent circuit (FIG. 2) of said autobiased resistor structure recited in claim 16 comprises:

• a V.sub.in terminal connected to said source of potential V.sub.in ;
• a V.sub.out terminal for providing said output potential V.sub.out ;
• a V.sub.GND terminal connected to said source of potential V.sub.GND ;
• a V.sub.CC terminal (ISO-SUBST.) connected to said source of potential V.sub.CC ;
• a resistor R1 connected between said V.sub.in terminal and said V.sub.out terminal;
• a resistor R2 connected between said V.sub.out terminal and said V.sub.GND terminal;
• a first diode D having an anode and a cathode, said anode of said first diode connected to said V.sub.in terminal;
• a second diode D1 having an anode and a cathode, said anode of said second diode connected to said V.sub.out terminal;
• a third diode D2 having an anode and a cathode, said anode of said third diode connected to said V.sub.CC terminal;
• a first capacitor C having a first terminal and a second terminal said first terminal connected to said V.sub.CC terminal;
• a second capacitor C2 having a first terminal and second terminal, said first terminal connected to said V.sub.CC terminal;
• and
• common connection means, connecting in common said cathode of said first diode D, said cathode of said second diode D1, said anode of said third diode, said second terminal of said first capacitor and said second terminal of said second capacitor,
• whereby said potential of said epitaxial layer of said autobiased resistor structure floats and has a magnitude corresponding to the potential of said common connection means, and said P type isolation wall and said P type substrate are maintained at said potential V.sub.CC.