Integrated circuit and method for biasing an epitaxial layer
AssigneeMotorola, Inc.
InventorsByron G. Bynum, David L. Cave
Life of this patent
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Abstract
An integrated circuit and method for biasing an impurity region, in particular an epitaxial layer, to a level substantially equal to a supply voltage level yet exhibiting a high reverse breakdown voltage to negative transients of the supply voltage. The integrated circuit and method is of especial utility in power BIMOS and other applications having the substrate at or near the supply voltage level.
Claims12
A circuit for biasing a first portion of an impurity region of an integrated circuit to a voltage level substantially equal to a supply voltage level comprising:
- a contact transistor formed within a second isolated portion of said impurity region and having first, second and third contact leads thereto, said first contact lead being coupled to a supply voltage line, said second contact lead being coupled to a bias voltage line and said third contact lead being connected to said first portion of said impurity region;
- and
- a shunt diode having anode and cathod terminals thereof, said anode and cathod terminals being respectively connected to said first and third contact leads of said contact transistor.
A method for biasing a first portion of an impurity region of an integrated circuit to a voltage level substantially equal to a supply voltage level while having a high reverse breakdown voltage to negative transients of said supply voltage level comprising the steps of:
- forming a contact transistor within a second isolated portion of said impurity region having first, second and third contact leads thereto;
- firstly coupling said first contact lead to a supply voltage line;
- secondly coupling said contact lead to a bias voltage line;
- connecting said third contact lead to said first portion of said impurity region;
- and
- providing a shunt diode having anode and cathode terminals thereof, said anode and cathode terminals being connected to said first and third contact leads of said contact transistor.
An integrated circuit including a circuit for biasing a first portion of an impurity region of said integrated circuit to a voltage level substantially equal to a supply voltage level while having a high reverse breakdown voltage to negative transients of said supply voltage level comprising:
- a contact transistor formed within a second isolated portion of said impurity region of said integrated circuit and having first, second and third contact leads thereto, said first contact lead being coupled to a supply voltage line, said second contact lead being coupled to a bias voltage line and said third contact lead being connected to said first portion of said impurity region;
- and
- a shunt diode having anode and cathode terminals thereof, said anode and cathode terminals being respectively connected to said first and third contact leads of said contact transistor.
Dependencies are inferred from the claim text.