Differential switch circuit

A differential switch circuit comprising:

• input means for receiving three or more distinct levels of an input signal and providing switch instructions respectively corresponding to said distinct levels, said input means including a high level comparator for detecting the highest level of said input signal to provide a high level instruction which is one of said switch instructions, a comparison level of said high level comparator being defined by a power supply potential of the switch circuit, said high level comparator including a first conductivity type first transistor whose emitter receives said power supply potential, whose base receives said input signal, and whose collector provides a first current corresponding to one of said switch instructions when the potential difference between the emitter and the base of said first transistor exceeds its base threshold voltage;
• bias means, coupled to said input means and being responsive to said switch instructions, for generating three or more bias signals respectively corresponding to said switch instructions, said bias means including a second conductivity type second transistor whose base receives said first current and whose emitter receives a circuit ground potential, and a first circuit containing serially connected resistive elements coupled between said power supply potential and said circuit ground potential, in which the juncture between two of said resistive elements is coupled to the collector of said second transistor, said juncture providing a first bias signal corresponding to one of said bias signals, said first bias signal having a first low potential when said first current is provided, and said first bias signal having a first high potential when said first current is not provided;
• and
• differential transistor means, coupled to said bias means and being responsive to said bias signals, for generating three or more outputs according to said bias signals, one of said outputs corresponding to one level of said input signal.

A differential switch circuit comprising:

• input means for receiving three or more distinct levels of an input signal and providing switch instructions respectively corresponding to said distinct levels, said input means including a high level comparator for detecting the highest level of said input signal to provide a high level instruction which is one of said switch instructions, a comparison level of said high level comparator being defined by a power supply potential of the switch circuit, said high level comparator including a first conductivity type first transistor whose emitter receives said power supply potential, whose base receives said input signal, and whose collector provides a first current corresponding to one of said switch instructions when the potential difference between the emitter and the base of said first transistor exceeds its base threshold voltage;
• bias means, coupled to said input means and being responsive to said switch instructions, for generating three or more bias signals respectively corresponding to said switch instructions, said bias means including a second conductivity type second transistor whose base receives said first current and whose emitter receives a circuit ground potential, and serially connected resistive elements coupled between said power supply potential and said circuit ground potential, in which the juncture between two of said resistive elements is coupled to the collector of said second transistor, said juncture providing a first bias signal corresponding to one of said bias signals, said first bias signal having a first low potential when said first current is provided, and said first bias signal having a first high potential when said first current is not provided;
• and
• differential transistor means, coupled to said bias means and being responsive to said bias signals, for generating three or more outputs according to said bias signals, one of said outputs corresponding to one level of said input signal.

A differential amplifier circuit with a differential switch circuit comprising:

• a first pair of differential transistors being equipped with a first switch transistor whose collector is coupled to the emitter of each of said first pair of differential transistors;
• a second pair of differential transistors whose collectors respectively coupled to the collectors of said first pair of transistors, said second pair being equipped with a second switch transistor whose collector is coupled to the emitter of each of said second pair of differential transistors;
• a third pair of differential transistors whose collectors respectively coupled to the collectors of said first pair of transistors, said third pair being equipped with a third switch transistor whose collector is coupled to the emitter of each of said third pair of differential transistors, wherein a load impedance coupled to one collector of said first pair of differential transistors is commonly used for the load of said second and third pairs of differential transistors;
• a constant current source coupled to each emitter of said first, second and third switch transistors;
• a first bias switch circuit being responsive to the level of a mode input applied thereto, for supplying the base of said first switch transistor with a first switching signal so as to conduct said first switch transistor when the level of said mode input is maximum;
• a second bias switch circuit being responsive to said mode input and to a bias input applied thereto, for supplying the base of said second switch transistor with a second switching signal so as to conduct said second switch transistor when the level of said mode input is medium and the level of said bias input is maximum;
• and
• a third bias switch circuit being responsive to said mode input and to said bias input, for supplying the base of said third switch transistor with a third switching signal so as to conduct said third switch transistor when the level of said mode input is minimum and the level of said bias input is maximum.

A differential switch circuit comprising:

• a first comparator having a first reference level equal to a power supply potential of said switching circuit, and being responsive to an input signal applied thereto, for comparing a level of said input signal with said first reference level and providing a first switch instruction when the input signal level exceeds said first reference level;
• a second comparator having a second reference level and being responsive to said input signal, for comparing a level of said input signal with said second reference level and providing a second switch instruction when the input signal level exceeds said second reference level which is lower than said first reference level;
• a third comparator having a third reference level and being responsive to said input signal, for comparing a level of said input signal with said third reference level and providing a third switch instruction when the input signal level falls down said third reference level which is lower than said first reference level;
• a first bias source coupled to said first comparator for generating a first bias signal which has a first high potential when said first switch instruction is provided, and which has a first low potential when said first switch instruction is not provided;
• a second bias source coupled to said second comparator for generating a second bias signal which has a second high potential when said second switch instruction is provided, and which has a second low potential when said second switch instruction is not provided;
• a third bias source coupled to said third comparator for generating a third bias signal which has a third high potential when said third switch instruction is provided, and which has a third low potential when said third switch instruction is not provided, said second high potential being lower than said first high potential and being higher than said first low potential or said third low potential, and said third high potential being higher than said first low potential or second low potential;
• a first switch transistor coupled at its base to said first bias source, for outputting from its collector a first output when said first bias signal has said first high potential;
• a second switch transistor coupled at its base to said second bias source, for outputting from its collector a second output when said second bias signal has said second high potential;
• a third switch transistor coupled at its base to said third bias source, for outputting from its collector a third output when said third bias signal has said third high potential;
• and
• a current source coupled to each emitter of said first, second and third switch transistors, for feeding these emitters with a given current.

A differential switch circuit comprising:

• input means for receiving an input signal which may assume three or more distinct levels and generating switching signals which respectively correspond to said distinct levels, signal, said input means including:
• first comparison means for generating a first switching signal when the level of said input signal is greater than a first reference level, said first reference level being equal to a power supply potential of said switching circuit and
• second comparison means for generating a second switching signal when the level of said input signal is greater than a second reference level, said second reference level being lower than said first reference level;
• bias means, connected to said input means, for generating three or more bias signals which respectively correspond to said switching signals;
• and
• switching means, connected to said bias means, for generating three or more output signals respectively corresponding to said bias signals.

A differential switch circuit comprising:

• first comparison means for receiving an input signal and comparing the level of said input signal with a first reference level corresponding to a power supply potential of said switch circuit and generating a first switching signal when the input signal level exceeds said first reference level;
• second comparison means for receiving said input signal and comparing the level of said input signal level with a second reference level corresponding to the ground potential of said switch circuit and generating a second switching signal when said input signal exceeds said second reference level;
• third comparison means for receiving said input signal and comparing its level with a third reference level which is less than said first reference level but greater than said second reference level, and generating a third switching signal when said input signal level falls below said first reference level;
• first bias means, connected to said first comparison means, for generating a first bias signal when said first switching signal is received;
• second bias means, connected to said second comparison means, for generating a second bias signal when said second switching signal is received;
• third bias means, connected to said third comparison means, for generating a third bias signal when said third switching signal is received;
• first switching means, connected to said first bias means, for generating a first output when said first bias signal is received;
• second switching means, connected to said second bias means, for generating a second output signal when said second bias signal is received;
• third switching means, connected to said third bias means, for generating a third output signal when said third bias signal is received;
• and
• current source means for providing current to each of said switching means.