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US 4,567,556 AGranted
Sequence controlling apparatus
AssigneeMatsushita Electric Works, Ltd.
InventorsToshiro Onogi, Kenichi Yoda, Masahiko Kitamura
Life of this patent
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Abstract
A sequence control apparatus includes a control unit and a memory unit detachably mounted to the control unit. The memory unit includes a memory device connected to an input circuit and an output circuit of the control unit via a pin connector. The memory device itself conducts logical operations in response to the input signals applied to the input circuit of the control unit.
Claims8
A sequence controlling apparatus including a control unit and a memory unit detachably mounted to the control unit,
- said control unit comprising:
- a body having a recess surrounded by a surrounding wall formed integrally with said body;
- a plurality of input terminals for receiving a plurality of input signals,
- an input circuit connected to said input terminals,
- an output circuit,
- a plurality of output terminals connected to said output circuit to supply said output signals, and
- a first connector connected to said input circuit and said output circuit;
- said memory unit comprising:
- a second connector selectively connected to said first connector to electrically connect said memory unit to said control unit,
- programmable read only memory means disposed in a case and being connected to said input circuit and said output circuit of said control unit via said second connector and said first connector for performing all sequence logical operations in response to said input signals and for providing sequence signals to said output circuit in response thereto, said programmable read only memory having an erasable portion;
- said case having a window positioned in juxtaposition to said erasable portion when said programmable read only memory is housed in said case, and
- said window being positioned such that incoming light is interrupted by said surrounding wall when said first and second connectors are connected to each other, whereby an undesired erasure of said erasable programmable read only memory is prevented.
9 more elements
Dependencies are inferred from the claim text.