Interruptable voltage-controlled oscillator and phase-locked loop using same

A phase-locked loop system, receiving a system reference signal, comprising:

• a voltage-controlled oscillator (VCO) circuit having an output terminal at which is supplied a VCO-output signal and having one or more emitter-coupled-logic (ECL) inverter stages connected as a ring oscillator, each ECL inverter stage having a respective first input terminal and a respective output terminal, each ECL inverter stage having a timing capacitor coupled between its output terminal and a first supply voltage, each ECL inverter stage having a first current source coupled between its output terminal and a second supply voltage, each first current source having a control terminal for varying its output current such that its output current controls the fall time of an output signal on the output terminal of the respective ECL inverter stage and such that the frequency of the ring oscillator is variable in response to control signals applied to the control terminals of the respective first current sources for the one or more ECL inverter stages;
• and
• phase-detector means having a first input terminal coupled to the output terminal of the VCO circuit for receiving the VCO-output signal, said phase-detector means having a second input terminal for receiving the system reference signal, said phase-detector means having an output terminal coupled to the control terminals of the respective first current sources of the one or more ECL inverter stages of the VCO circuit, said phase-detector means for providing a VCO-control signal proportional to the difference in phase between the system reference signal and the VCO-output signal at the output terminal of the phase-detector means.

The system for discriminating an input pulse width comprising:

• an inverter coupled to receive the input pulse and to generate an inverted input pulse at its output;
• a first ECL noninverting stage having an output terminal and having an input terminal coupled to the output of the inverter for receiving the inverted input pulse;
• a first delay-timing capacitor coupled between the output terminal of the first ECL noninverting stage and a first supply voltage;
• a first delay-current source coupled between the first ECL noninverting stage and a second supply voltage, said first delay-current source having a control terminal for varying its output current and the control terminal coupled to receive the control signal, with fall time of the signal on the output terminal of the first ECL noninverting stage being proportional to the control signal;
• a second ECL noninverting stage having an output terminal and having an input terminal for receiving the input pulse;
• a second delay-timing capacitor coupled between the second ECL noninverting stage output terminal and the first supply voltage;
• a second-delay-current source coupled between the second ECL noninverting stage and the second supply voltage said second delay-current source having a control terminal for varying its output current coupled the control signal with the fall time of a signal on the output terminal of the second ECL noninverting stage being proportional to the control signal;
• a second hysteresis circuit having an output terminal and having an input terminal coupled to the output terminal of the second ECL noninverting stage, said second hysteresis circuit providing at its output terminal a pulse having a variable width proportional to the control signal;
• wherein the first delay-timing capacitor has a larger capacitance value than the second delay-timing capacitor.

An ECL gate having an output terminal and an inverting-input terminal and having a controlled fall time, including:

• a timing capacitor coupled between a first voltage source and the output terminal;
• a first current source coupled between the output terminal and a second voltage source, said first current source having a control input terminal for controlling the current provided by said first current source;
• an output driver transistor having an emitter terminal coupled to the output terminal, a collector terminal coupled to the first voltage source, and a base terminal coupled through a first resistance element to the first voltage source;
• an inverting-input transistor having a collector coupled to the base terminal of the output driver transistor, an emitter coupled through a second current source to the second voltage source, and a base terminal coupled to the inverting-input terminal;
• and
• said first current source having its output current controlled by a signal on its control input terminal to control the current charging the timing capacitor and thereby control the fall time of the output signal on the output terminal.

A system for producing a receiver clock reference signal from a received signal and receiving a system reference signal, comprising:

• a first voltage-controlled oscillator (VCO) having an output terminal and a first VCO frequency-control terminal, and providing a first VCO output signal at its output terminal, the frequency of the first VCO output signal being proportional to a first VCO control voltage applied at the first VCO frequency-control terminal;
• wherein
• the first VCO includes at least one emitter-coupled-logic (ECL) inverter stage, each ECL inverter stage having an input terminal and an output terminal, a timing capacitor coupled between its output terminal and a first supply voltage, and a controllable current source coupled to supply current at its output terminal, the controllable current source being coupled to the first VCO frequency-control terminal and including a means responsive to the first VCO control voltage for controlling its output current;
• a first phase detector having a first input terminal coupled to the output terminal of the first VCO for receiving the first VCO output signal and having a second input terminal for receiving the system reference signal, said first phase detector having an output terminal coupled to the first VCO frequency-control terminal and providing the first VCO control voltage at its output terminal for locking the frequency of the first VCO output signal to the frequency of the system reference signal;
• a second VCO, having an output terminal, a second VCO frequency-control terminal coupled to the first VCO control voltage and a phase-control terminal, and providing the receiver clock reference signal at its output terminal;
• and
• a second phase-detector having a first input terminal coupled to the output terminal of the second VCO, having a second input terminal coupled to receive the received signal, and having an output terminal coupled to the phase-control terminal of the second VCO, said second phase detector for providing a second VCO control voltage at its output terminal for locking the phase of the receiver clock reference signal to the phase of the received signal, whereby the frequency of the receiver clock reference signal is bounded in its frequency range by the first VCO control voltage and the phase of the receiver clock reference signal is independently controlled by the second VCO control voltage.