US 4,564,794 AGranted

Phase locked loop and a motor control servo

AssigneeInternational Business Machines Corporation

InventorsRichard S. Kilen, Larry E. Rittenhouse

Life of this patent

Estimating the term…

Loading patent…

Abstract

The speed of a DC motor (10) is controlled by a servo which includes a digital phase lock loop. The motor drives a tachometer whose pulse (22) frequency is low relative to the frequency of a clock (21). The clock continuously drives a counter (200) whose ever increasing number content is gated to a data latch (26) upon the occurrence of each successive tachometer pulse, thus this data latch contains a first time-number of ever increasing magnitude. A second data latch (24) contains a second number. The difference in magnitude of two consecutive time-numbers is indicative of motor speed. Initially, this second number is set to contain a reference number (REF) which is equal in magnitude to the number of clock pulses which will occur between adjacent tachometer pulses when the motor is running at desired speed. A pair of limit numbers (RANGEL and RANGEH) are provided to define the upper and lower limits of servo saturation. The difference between the first number and the second number is detected upon the occurrence of each tachometer pulse to generate a third or difference number (ERRA). This difference number is compared to the two limit numbers to determine if the servo is in saturation. If it is not in saturation, the second number is reset to a value which is equal to the old value plus the reference number. If the servo is in saturation, the second number is reset to a number which is a function of the first number, the reference number, and that limit number which is associated with the particular mode of saturation.

Claims13

Dependent claims

A phase lock loop, comprising:

a high frequency clock (21),
a counter (200) driven by said clock,
a low frequency source (22) of a repeating input pulse (TACH),
a first data latch (26) controlled by said input pulse and operative to receive the numerical content of said counter upon the occurrence of each of said input pulses,
a reference number (REF) whose magnitude is indicative of the number of high frequency clock pulses which should occur between each pulse of said low frequency source,
a second data latch (24) initially containing said reference number,
digital phase detector means (27) receiving as input the content of said first and second data latches, and providing an output signal (ERRA) indicative of the numeric difference which exists between these two inputs,
range defining means operable to generate a high magnitude number (RANGEH) defining an upper limit of numeric difference, and a low magnitude number (RANGEL) defining a lower limit of numeric difference,
testing means (34, 36 and 35) receiving said high and low limit numbers and the numeric difference output of said phase detector means,
said testing means generating an output number which is directly related to said numeric difference when said difference lies between the upper and lower limits which are defined by said high and low magnitude numbers, respectively,
and generating an output number which is directly related to the upper and lower limits, respectively, when said numeric difference is above or below the limits defined by said high and low magnitude numbers, respectively, and
reset means (46 and 50) responsive to said testing means determining that said numeric difference is above or below the limits defined by said high and low magnitude numbers, and operable in response thereto to reset the number content of said second data latch in a manner intended to bring said numeric difference within the range defined by said upper and lower limits upon the occurrence of a subsequent input pulse.

9 more elements

A digital phase lock loop, comprising:

a source (26) of an input first number (TEDGE) whose magnitude represents the passage of time,
a resettable source (24) of a reference second number (NREF),
phase detector means (27) receiving said first and second numbers as an input, and providing an output number (ERRA) indicative of the difference which exists between the two input numbers,
range defining means operable to generate a third number (RANGEH) defining an upper limit of said difference, and a fourth number (RANGEL) defining a lower limit of said difference,
testing means (34, 35 and 36) receiving said second, third and fourth numbers as inputs, and generating an output number (ERR),
said testing means generating a fifth number which is directly related to said difference when said difference lies between the upper and lower limits which are defined by said third and fourth numbers, respectively,
and generating a sixth number which is directly related to the third and fourth numbers, respectively, when said difference is above or below the limits defined by said third and fourth numbers, respectively, and
reset means (46 and 50) responsive to said testing means generating said sixth number, and operable in response thereto to reset said second number in a manner intended to bring said difference with the range defined by said third and fourth numbers upon the occurrence of a subsequent first number.

5 more elements

A phase lock loop motor speed servo, comprising:

a variable speed motor,
a tachometer driven by said motor and constituting a repeating pulse (TACH), the period of which is indicative of motor speed,
a constant frequency clock (21 and 200),
a latch (26) controlled by said tachometer, and operable upon the occurrence of a tachometer pulse to latch the total number of clock cycles,
a number source (23) defining the first reference number (REF), said first reference number defining the number of cycles of said clock which will occur when said motor is running at a predetermined speed,
an adder circuit (50) receiving as one of two inputs said reference number, and generating a second reference number (NREF) therefrom,
phase detector means (27) receiving as inputs the content of said latch and said second reference number, and providing an output (ERRA) indicative of the difference which exists between the two inputs,
range defining means operable to define an upper limit (RANGEH) and a lower limit (RANGEL) of difference,
testing means (34, 35 and 36) receiving as input said limits and the output of said phase detector means,
said testing means generating a motor energization output signal which is directly related to said difference when said phase difference lies within said upper and lower limits,
and generating a motor energization output signal which is directly related to said upper and lower limits when said difference is outside of said limits,
reset means (46) responsive to said testing means determining that said difference is outside of said limits, and operable in response thereto to provide a second input to said adder means, to thereby control said second reference number as a function of said upper and lower limits upon the occurrence of subsequent tachometer pulse, and
means connecting said motor energization output signal to said motor.

10 more elements

Dependencies are inferred from the claim text.