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US 4,560,921 AGranted
Comparator circuit with built in reference
AssigneeNational Semiconductor Corporation
InventorMineo Yamatake
Life of this patent
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Abstract
A comparator circuit is disclosed wherein the input terminals are provided with a predetermined reference potential. Thus, in the case where only one input is driven the other input is biased at close to the reference. In the application of the circuit it is not necessary to provide an external package pin for reference potential.
Claims10
A comparator circuit having a pair of differential signal input terminals, a single-ended output and an input biasing circuit, said input bias circuit comprising:
- current sink means coupled to said signal input terminals;
- current source means coupled to said signal input terminals;
- and
- means, responsive to the common mode potential at said signal input terminals, for controlling one of said current sink means and said current source means, to produce a reference bias at said signal input terminals.
1 more element
Dependencies are inferred from the claim text.