US 4,559,608 A · Arithmetic logic unit

Abstract

An ALU having improved propagate and generate signal section as well as carry and sum logic section to decrease the propagation delays. The propagate and generate signal section is specifically designed to be used with a dual ported RAM such that transition of the precharged RAM outputs to the desired outputs are used to trigger the logic. Latches, which are an integral part of the output of the propagate and generate signal section and are latched by the high/low transition of the output and reset by precharge signal, are used in combination with a special control sequence of the logic select of the propagate and generate section to isolate the latch and output such that one of the buses though the ALU may be used as a bidirectional bus so that the ALU may write back into the RAM without intermediate registers or latches. To reduce the length of interconnects and number of crossovers when the ALU includes a shifter/swapper for BCD operations, the carry and sum logic units are grouped by nibbles and are interleaved. Also, the carry and sum logic of nibbles other than the first nibble have carry look ahead logic such that only a single delay is experienced per nibble to produce a carry nibble. The delay of the logic sections are reduced by precharging the drain of each of the FETs in the input logic.

Claims29

Dependent claims

In an arithmetic logic unit having a first section for producing a propagate and a generate output signals from a pair of input variables per bit and logic select signals provided thereto, and a second section for producing a carry and a sum output signal from said propagate and generate signals, the improvement comprising:

first precharge means in said first section for precharging the propagate and generate output signal to a first logic level in response to precharge signals;
first latch means integral with said arithmetic logic unit and responsive to a transition of said propagate output signal from said first logic level to a second logic level for maintaining said propagate signal at said second logic level until the next precharge signal;
and
second latch means integral with said arithmetic logic unit and responsive to a transition of said generate output signal from said first logic level to a second logic level for maintaining said generate output signal at said second logic level until the next precharge signal.

1 more element

In a carry and sum logic unit for a plurality of bits including for each bit a carry means for producing a carry-out signal as a function of a carry-in signal, a propagate signal and generate signal, and a sum means for producing a sum signal as a function of said carry-in signal and said propagate signal, the improvement comprising:

said carry means of said first four bits being connected in series without carry look ahead, a carry-in to the first bit requires four logic delays to propagate to the output of the fourth bit carry means as a nibble carry;
and
said carry means of the fifth and subsequent bits being connected in series with carry look ahead means for a nibble of four bits, a carry-in to the first bit of the nibble requires one logic delay to propagate a nibble carry to the output of the fourth bit of the nibble.

A logic gate comprising:

a first switch means having an input terminal connected to a first logic level source, an output terminal and a control terminal which is an input of said gate and controls the conduction between said input and output terminals of said first switch means;
a second switch means having an input terminal connected to the output terminal of said first switch means, an output terminal which is the output of said gate, and a control terminal which is another input of said gate and controls the conduction between said input and output terminals of said second switch means;
a first precharge means connected to said output terminal of said first switch means for precharging said output terminal of said first switch means to a second logic level;
and
a second precharge means connected to said output terminal of said second switch means for precharging said output terminal of said second switch means to said second logic level.

2 more elements

A logic gate comprising:

a first switch means having an input terminal connected to a first logic level source, an output terminal which is the output of said gate and a control terminal which is an input of said gate and controls the conduction between said input and output terminals of said first switch means;
a first precharge means connected to said output terminal of said first switch means for precharging said output terminal of said first switch means to a second logic level;
and
a maintaining means connected to said output of said gate for maintaining said gate output at said second logic level after deactivation of said first means except when said first switch means is conducting.

1 more element

Dependencies are inferred from the claim text.

Arithmetic logic unit

Life of this patent

Arithmetic logic unit

Life of this patent

Abstract

Claims29