Digital signal processing system employing logarithms to multiply and divide

A digital signal processing system for processing a first number and a second number to produce a result number comprising:

• first memory means for producing N-bit logarithms of said first and said second numbers from a table of N-bit logarithms to a base B stored therein;
• combining means coupled to said first memory means for combining the N-bit logarithms of said first and said second numbers;
• and
• second memory means including a table of antilogarithms to said base B for producing said result number in response to said combination of the N-bit logarithms of said first and said second numbers,
• wherein said base B is selected in accordance with the magnitudes of said result numbers to utilize substantially the entire range of possible magnitudes of said N-bit logarithms.

A digital signal processing system for multiplying a multiplier number and a multiplicand number to produce a product number comprising:

• first memory means for producing N-bit logarithms of said multiplier and said multiplicand numbers from a table of N-bit logarithms to a base B stored therein;
• combining means coupled to said first memory means for adding the N-bit logarithms of said multiplier number and said multiplicand number;
• and
• second memory means for producing from a table of antilogarithms to said base B stored therein said product number in response to the sum of the N-bit logarithms of said multiplier and said multiplicand numbers produced by said combining means,
• wherein said base B is selected in accordance with the magnitudes of said product numbers to utilize substantially the entire range of possible magnitudes of said N-bit logarithms.

A digital signal processing system for dividing a dividend number by a divisor number to produce a quotient number comprising:

• first memory means for producing N-bit logarithms of said dividend and said divisor numbers from a table of N-bit logarithms to a base B stored therein;
• combining means coupled to said first memory means for subtracting the N-bit logarithm of said divisor number from that of said dividend number;
• and
• second memory means for producing from a table of antilogarithms to said base B stored therein said quotient number in response to the difference of the N-bit logarithms of said dividend and said divisor numbers,
• wherein said base B is selected in accordance with the magnitudes of said differences to utilize substantially the entire range of possible magnitudes of said N-bit logarithms.

A digital signal processing system for multiplying a multiplier number and a multiplicand number to produce a product number comprising:

• first addressable memory means for producing N-bit logarithms of said multiplier and said multiplicand numbers, including a plurality of addressable cells storing logarithms corresponding to the logarithms to a base B of the addresses thereof, said base B being selected dependent on the maximum possible magnitudes of said product numbers to utilize substantially the entire range of magnitudes of said N-bit logarithms;
• multiplexing means for sequentially applying said multiplier and said multiplicand numbers to said first addressable memory means;
• storing means coupled to said first addressable memory means and cooperating with said multiplexing means for storing the logarithms to said base B of one of said multiplier and said multiplicand numbers;
• adding means coupled to said storing means and to said first addressable memory means, for summing said logarithms of said mutliplier and said multiplicand numbers produced by said storing means and by said first addressable memory means;
• and
• means including a second addressable memory means, coupled to said adding means, for producing said product numbers in response to said summed logarithms produced by said adding means, said second addressable memory means including a plurality of addressable cells storing antilogarithms corresponding to the antilogarithms to said base B of the addresses thereof.

A digital signal processing system for multiplying a multiplier number and a multiplicand number, both of which are in a signed number format, to produce a signed product number comprising:

• formatting means having an input to which numbers in said signed number format are applied and having an output at which corresponding unsigned magnitude numbers are produced;
• first addressable memory means having an address input to which the output of said formatting means is coupled, having a plurality of addressable cells each storing an N-bit logarithm to the base B of the address thereof, and having an output at which the N-bit logarithms stored in said addressable cells addressed by said unsigned magnitude numbers are produced, wherein said base B is selected dependent on the possible values of said product numbers to utilize substantially the entire range of possible magnitudes of said N-bit logarithms;
• means for applying said multiplier and said multiplicand numbers to the input of said formatting means, whereby the logarithms to said base B thereof are produced at the output of said first addressable memory means;
• adding means coupled to said first addressable memory means for adding said logarithms to said base B of said multiplier and said multiplicand numbers to produce logarithm sums;
• second addressable memory means having an address input to which said adding means is coupled, having a plurality of addressable cells each storing an antilogarithm to said base B of the address thereof, and having an output at which the antilogarithms to said base B stored in said addressable cells addressed by said logarithm sums are produced;
• signing means receiving sign indicating portions of said multiplier and said multiplicand numbers for developing a sign indication of said product number;
• reformatting means having respective inputs to which said produced antilogarithms and said sign indication are applied for producing at an output thereof said signed product number;
• and
• detecting means having an input to which said multiplier and said multiplicand numbers are applied, and having an output for producing an indicating signal in response to either of said multiplier and multiplicand numbers having zero magnitude;
• and
• means coupled to said reformatting means and said detecting means for making said signed product number having zero magnitude in response to said indicating signal.