Charge transfer device operative at high speed

A charge transfer device formed on a semiconductor substrate comprising:

• first, second and third input terminals receiving first, second and third clock pulses, said first, second and third clock pulses having different phases so that said first, second and third pulses are generated in the order, first, second and third, respectively;
• first, second and third resistors having one end connected with said first, second and third input terminals, respectively;
• first, second and third signal lines connected with the other ends of said first, second and third resistors, respectively;
• a plurality of transfer gates arranged in a line, said transfer gates, except for a final stage transfer gate, being connected with said first, second and third signal lines, respectively, so that said transfer gates connected with said first, second and third signal lines are repeatedly disposed in this order;
• a fourth signal line connected with said final stage transfer gate;
• a fourth resistor inserted between said fourth signal line and a predetermined one of said first, second and third input terminals so that the line of said transfer gates including said final stage transfer gate repeatedly receives said first, second and third clock pulses in this order;
• an output gate disposed adjacent to said final stage transfer gate, said output gate receiving a constant voltage;
• and
• a detection means for producing a output signal in response to charges transferred thereinto from a region of said semiconductor substrate under said output gate.

A charge transfer device on a semiconductor substrate comprising;

• a pulse generator generating a plurality of first clock pulses, said first clock pulses having different phases with one another, said pulse generator further generating a second clock pulse having the same phase as one of said first clock pulses;
• a plurality of first signal lines each receiving a corresponding one of said first clock pulses, respectively;
• a second signal line receiving said second clock pulse;
• plural sets of transfer gates arrayed in a line, said transfer gates belonging to different sets being disposed side by side in predetermined order such that said predetermined order of said sets is repeated, said transfer gates belonging to the same sets except for a final stage transfer gate and being connected with a corresponding one of said first signal lines, respectively, so that said transfer gates repeatedly receive said first clock pulses in a predetermined order of said first clock pulses, said final stage transfer gate being connected to said second signal line;
• and
• a detection means disposed adjacent to said final stage transfer gate for producing an output signal.

A system for operating a charge transfer device comprising:

• a pulse generator generating first, second and third clock pulses having phases different from one another and a fourth clock pulse, said phase of said first clock pulse being advanced relative to said second and third clock pulses, said phase of said third clock pulse being late relative to said first and second clock pulses, and said fourth clock pulse having a leading edge synchronized with a leading edge of said first clock pulse and a falling edge synchronized with a leading edge of said second clock pulse;
• a charge transfer device having a plurality of transfer gates arrayed in a line and an output detection means for producing an output signal from charges transferred from a final stage transfer gate;
• a first means for applying said first clock pulse to every third transfer gate, except for said final stage transfer gate;
• a second means for applying said second clock pulse to every third transfer gate, except for said final stage transfer gate, starting with a transfer gate located next to a said transfer gate to which said first clock pulse is applied;
• a third means for applying said third clock pulse to every third transfer gate, except for said final stage transfer gate starting with a transfer gate located between a said transfer gate to which said second clock pulse is applied and a said transfer gate to which said first clock pulse is applied;
• and
• a fourth means for applying said fourth clock pulse to said final stage transfer gate.