Cutting insert with means for simultaneously removing a plurality of chips
AssigneeGeneral Electric Company
InventorsRanga Komanduri, William R. Reed, Jr.
Life of this patent
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Abstract
A cutting insert presents clearance and rake faces constructed and dimensionally interrelated to provide a plurality of adjacent offset, substantially parallel, non-coplanar cutting edges. The offset is in the range of from about 0.010 to 0.100 inch and the planes along the clearance face, which include the cutting edges, form part of a series of steps defined by intersecting planes. Each of the angles between these intersecting planes has a value of at least about 90 degrees.
Claims7
A polygonal cutting insert comprising first and second spaced substantially parallel opposed primary faces, a plurality of side faces generally perpendicular to said primary faces connecting said primary faces, at least one corner formed by the intersection of said first primary face and two of said side faces, at least three discrete substantially parallel cutting edges at said corner formed adjacent the intersection of said two side faces and said first primary face, at least two of said cutting edges being staggered inwardly to a different extent in a direction parallel with said first primary face and at least one of said cutting edges being staggered inwardly in a direction perpendicular to said first primary face.
Dependencies are inferred from the claim text.