Response detector for pattern processing system

Abstract

A pattern processing system associates image input patterns with desired response codes. The image input is stored in an image buffer as an addressable array of sample values. An address sequencer provides an address stream containing a plurality of interleaved sequences of addresses to the image buffer and to a read/write response memory. The next address of each sequence provided by the address sequencer is based upon the current address of that sequence and the state of the sample value stored in the image buffer at the location corresponding to the current address. Once the address sequencer repeats an address in a sequence, that address sequence is in a repetitive address loop as long as the image stored in the image buffer remains constant. During a training mode, a pattern to be recognized is supplied to the image buffer and a training code representing a desired response is written into the response memory at selected locations that correspond to addresses in the address loop being generated. During a later recognition mode, when the same pattern is supplied to the image buffer, the same address loop is again generated. The previously stored training codes are read from the response memory. A response detector forms a histogram of the codes read out during an integration interval. Based upon this histogram, the response detector provides a response code output representative of the pattern based upon the most frequent code (or codes) read out from the response memory.

Dependencies are inferred from the claim text.