US 4,550,292 A · Automatic oscillator frequency control system

Abstract

A frequency control system is provided which makes an initial correction of the frequency (f.sub.CLK) of its own timing circuit (50, 52, 54, 56) after comparison against a frequency (f.sub.REF) of known accuracy and then sequentially checks and corrects the frequencies of several voltage (13a . . . 13e) controlled local oscillator circuits (12a . . . 12e). The timing circuit initiates the machine cycles of a central processing unit (30) which, over a sampling interval having a duration of a fixed number of machine cycles, applies a frequency index (FI) to an input register (22) in a modulo-sum frequency divider stage (20) and enables a multiplexer (16) to clock an accumulator register (26) in the divider stage (20) with a cyclical signal derived from the oscillator circuit being checked. Upon expiration of the interval, the processing unit (30) compares the remainder (FN) held as the contents of the accumulator (26) against a stored zero-error constant and applies an appropriate correction word (CW) to a correction stage (60a, 62a, . . . 64a, . . . 60e, 62e, 64e) to shift the frequency of the oscillator being checked. A signal taken from the accumulator register (26) may be used to drive a phase plane ROM (94) and, with periodic shifts in the applied frequency index (FI), to provide frequency shift keying of the applied resultant output signal. Interposition of the phase adder (90) between the accumulator register (26) and phase plane ROM (94) additionally permits phase shift keying of the output signal by periodic variation in the value of a phase index (PI) applied to one input port of the phase adder (90). An overflow signal may be taken from an adder (24) in the frequency divider stage (20) to drive an auxiliary counter (120) to provide a prescaling number which can be used by the central processing unit (30) to expand the correction range of the control system.

Claims16

Dependent claims

A frequency control system, comprising:

divider means (20) including a register (26) having n-bits of binary capacity and means (24) for incrementing the contents of said register with a first number in response to reception of each pulse of a cyclical signal;
programmable processing means (30) interconnected with said divider means and operable in sequential machine cycles for generating said first number and second number during an interval set by a fixed number of said machine cycles wherein said first number and said second number correspond to an assigned frequency and are employed for comparing the contents of said register (26) with a predetermined number upon termination of said interval, and further, are employed for propagating a correction signal determined by any difference between said contents and said predetermined number;
a source (12a/12e, 14a/14e, 66a/66e) providing a cyclical signal with a characteristic frequency that is correctable by reception of a shifting signal;
switching means (16) connectable to said source, operatively enabled during reception of said second number to apply said cyclical signal to said divider means;
converting means (60a/60e, 62a/62e, 64a/64e) operatively responsive to said processing means for applying said shifting signal to said source upon reception of said correction signal;
and
timing means (50, 52, 54, 56, 66f) coupled to said processing means for initiating each of said machine cycles, whereby after said termination of said interval, said contents of said register (26) contain a modulo-(2.sup.n .multidot.Q) sum representing the product of said first number, said characteristic frequency, the duration of said interval, and 2.sup.-n, thereby enabling said programmable processing means to gauge any variation in the product of the period of said machine cycles and said characteristic frequency by comparing said sum to said predetermined number, to use said variation to determine the value of said correction signal, and to apply said correction signal to said converting means.

4 more elements

A frequency control system, comprising:

programmable processing means (30) including a memory (38, 40) and a routine stored in said memory for controlling the operation of said frequency control system;
said memory containing, for a source providing a cyclical signal having a characteristic frequency connectable to said system, a selection word, index number, and ideal count corresponding to the assigned frequency of said source;
said processing means providing to said system during a sampling interval, a selection word and index number corresponding to said source, and after said sampling interval for comparing the corresponding ideal count stored in memory with n least-significant bits of a digital count made during said interval and propagating a correction number determined by any difference between said ideal count and said n least-significant bits of said digital count;
means (20) interconnected with said programmable processing means for incrementing said index number once per cycle of said characteristic frequency to make said digital count while being clocked by said cyclical signal, said incrementing means having a register (26) with n bits of binary capacity, for retaining said n least-significant bits of said digital count;
means (16) connectable to said source providing a cyclical signal having said characteristic frequency and enabled by said selection word for clocking said incrementing means with said cyclical signal;
means (60a . . . 60f, 62a . . . 62f, 64a . . . 64f, 66a . . . 64f) connectable to said source and operatively responsive to said processing means for shifting said characteristic frequency upon reception of said correction number;
and
timing means connectable to said processing means and shifting means for regulating the duration of said interval.

5 more elements

A frequency control system, comprising:

a programmable central processing unit (30) containing a memory (38, 40) and a routine stored in said memory for controlling operation of said frequency control system in sequential machine cycles, said memory including a selection word, a plurality of frequency index numbers, a plurality of phase index numbers, and an ideal count;
said processing means providing to said system said selection word and selected ones of said frequency and said phase index numbers and propagating a correction word determined by comparison of said ideal count and with the contents of an n-bit register upon expiration of a sampling interval set by a fixed number of said machine cycles;
a frequency divider (22, 24, 26), including said n-bit register, interconnected with said processing unit and cyclically incrementing the contents of said n-bit register when clocked by a cyclical signal;
switching means (16) connectable to a source providing a cyclical signal, said source having an electrically variable characteristic frequencies, said clocking means being operatively enabled during reception of said second number to apply said cyclical signal to said divider means;
a timing circuit (50, 52, 54, 56) including a voltage controllable oscillator exhibiting a characteristic frequency, providing a timing signal initiating each of said machine cycles;
means (60a . . . 60f, 62a . . . 62f, 64a . . . 64f, 66a . . . 66f) connectable to said processing means for shifting a selected one of said source generated characteristic frequencies upon reception of said correction signal;
a first adder (90) interconnected to said n-bit register and said processing unit to continuously generate the sum of the contents of said register and said one of said phase index numbers;
a memory (94) containing sequential components of a time varying waveform addressable by said sum;
and
means (96) for converting said sequential components into a time varying analog signal.

7 more elements

Dependencies are inferred from the claim text.

Automatic oscillator frequency control system

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Automatic oscillator frequency control system

Life of this patent

Abstract

Claims16