Repairable multi-level overlay system for semiconductor device
AssigneeInternational Business Machines Corporation
InventorsMario E. Ecker, Leonard T. Olson
Life of this patent
Estimating the term…
Abstract
A multi-level integrated circuit packaging system having a primary support frame, an array of secondary support frames mounted in said primary support frame and an array of single chip carriers associated with each secondary support frame. An integrated circuit is encapsulated in each single chip carrier, which may be a variety of carrier types which has an insulated wiring pattern with EC wells and delete lands. The secondary and primary support frames also have EC pads so that a change capability exists to any electrical signal path terminating on the chip.
Claims18
A multi-level integrated packaging structure for supporting and electrically interconnecting a plurality of integrated circuit chips comprising:
- a primary planar support frame having a primary array of spaced areas, a wiring pattern disposed on said primary planar support frame providing connection contacts, engineering change wiring channels and contacts in spaces on said primary array between said spaced areas;
- a plurality of secondary planar support frames equal in number to said spaced areas defining said spaced primary array, said plurality of secondary planar support frames being respectively positioned within said primary array, each of said secondary planar support frames having a secondary array of spaced areas, each of said secondary planar support frames containing a wiring pattern providing connection contacts, engineering change wiring channels and contacts in spaces on said secondary array between said secondary array of spaced areas;
- a plurality of substantially planar single chip carriers disposed on said secondary arrays, each of said chip carriers containing at least an integrated circuit chip and having an array of exposed connection contact means, and containing wiring for electrically interconnecting said integrated circuit chip to said array of exposed connection contacts on said same single chip carrier;
- first connection means for connecting each of said single chip carriers to predetermined connection contacts on said secondary planar support frames, and;
- second connection means for connecting predetermined contacts of said secondary planar support frames to predetermined connection contacts of said primary planar support frame whereby repair and replacement of single chip carriers and engineering wiring changes are facilitated.
An improved multi-level integrated packaging structure for supporting and electrically interconnecting a plurality of integrated circuit chips comprising:
- a tiered support structure having a primary support frame, a plurality of secondary planar support frames mounted on said primary support frame and a plurality of single chip carriers mounted on said secondary support planar frames;
- said primary support frame and each of said secondary support frames having a wiring pattern providing connection contacts, engineering change wiring channels and contacts thereon;
- integrated circuit chips mounted on said single chip carriers, said chip carriers having exposed contact means and, wiring for electrically interconnecting said integrated circuit chip to said contact means;
- first connection means for connecting predetermined contacts of said single chip carriers to predetermined connection contacts on said secondary planar support frames, and;
- second connection means for connecting predetermined contacts of said secondary planar support frames to predetermined contacts of said primary planar support frame.
Dependencies are inferred from the claim text.