High speed charge balancing comparator
AssigneeIntersil Corporation
InventorDavid Bingham
Life of this patent
Estimating the term…
Abstract
A high speed charge balancing comparator in which, without loading or affecting its input, the internal nodes and output node are maintained at voltage levels at or very close to their autozero values until a time after the commencement of the compare phase such that the polarity of the voltage at the input charge balancing node is correct. The comparator is of the type for comparing two or more voltages including a gain stage having an input node responsive to the voltages, plural internal nodes and an output node, and a plurality of switches for sequencing the voltages to the input nodes during alternate autozero and compare phases. Switches maintain the gain stage internal nodes and output node at voltage levels close to their values during the autozero phase until a time after the commencement of the compare phase.
Claims14
A comparator for comparing two or more input voltages comprising:
- an amplifier having an input node, at least one internal node, and an output node;
- means for operating said amplifier in alternate autozero and compare phases in which said input, internal and output nodes are driven to respective autozero voltages during said autozero phase, and at least two input voltages are compared at said input node during said compare phase;
- switch means having an open state and a closed state for coupling said output node to said internal node when closed;
- and
- means for maintaining said switch means closed during said autozero phase and until a predetermined time after the commencement of said compare phase to maintain said amplifier internal node and output node at voltage levels close to their autozero values during said autozero phase and until a predetermined time after the commencement of said compare phase.
A comparator for comparing two or more input voltages comprising:
- an amplifier comprising two field-effect transistor gain stages, said amplifier having an input node coupled to the gate of the first transistor gain stage, an internal node coupled to the output of the first transistor stage and the gate of the second transistor stage and an output node coupled to the output of the second transistor gain stage;
- means for operating said amplifier in alternate autozero and compare phases in which said input, internal and output nodes are driven to respective autozero voltages during said autozero phase, and at least two input voltages are compared at said input node during said compare phase;
- and
- means for maintaining said amplifier internal node and output node at voltage levels close to their respective autozero values during said autozero phase and until a predetermined time after the commencement of said compare phase so that any voltage transient at the input node during the predetermined time is suppressed at the internal node.
A comparator for comparing two or more input voltages comprising:
- an amplifier comprising three cascaded gain stages, each gain stage having an input and an output, said amplifier having an input node coupled to the input of the first gain stage, an internal node coupled to the output of the first gain stage and the input of the second gain stage, and an output node coupled to the output of the third gain stage;
- at least two input capacitors coupled to the input node at one end, the other end of each capacitor having a plurality of transistor switches associated therewith for sequentially coupling the associated capacitor to a plurality of input voltages;
- a first feedback transistor switch for coupling the output to the input of the first gain stage during an autozero cycle;
- a second feedback transistor switch for coupling the output to the input of the second gain stage during the autozero cycle;
- and
- a third feedback transistor switch for coupling the output to the input of the third gain stage;
- a fourth feedback transistor switch for coupling the amplifier output node to the amplifier internal node during the autozero cycle;
- and
- means for maintaining the third and fourth transistor switches in a closed state for an interval of time after the termination of the autozero phase to allow substantial settling voltage transients at the amplifier input node before the third and fourth transistor switches are opened.
Dependencies are inferred from the claim text.