Semiconductor device having contacting but electrically isolated regions of opposite conductivity types
AssigneeTokyo Shibaura Denki Kabushiki Kaisha
InventorHideharu Egawa
Life of this patent
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Abstract
A semiconductor device includes p- and n-type semiconductor layers formed on an insulating substrate and gate electrodes selectively and insulatively formed over the respective p- and n-type semiconductor layers and forming D-type MOS transistors. In this semiconductor device, the p- and n-type semiconductor layers are made in contact with each other, and negative and positive power supply terminals which are respectively set at negative and positive potentials are respectively connected to the p- and n-type semiconductor layers thereby to electrically isolate the p-type and n-type semiconductor layers from each other.
Claims11
A semiconductor circuit comprising:
- first, second and third power supply terminals which are respectively set at first, second and third voltage potentials of different levels said third voltage potential being at a level between the levels of said first and second voltage potentials;
- a first semiconductor circuit section connected to said first power supply terminal for generating an output signal having a voltage potential level between said first voltage potential and said third voltage potential according to an input signal having a voltage potential level between said second and third voltage potentials;
- and
- a second semiconductor circuit section connected to said second power supply terminal for generating an output signal having a voltage potential level between said second and third voltage potentials according to the output signal from said first semiconductor circuit section.
Dependencies are inferred from the claim text.