Self-aligned manufacture of FET
AssigneeHitachi, Ltd.
InventorsKiichi Ueyanagi, Yasunari Umemoto, Susumu Takahashi, Michiharu Nakamura
Life of this patent
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Abstract
This specification discloses a self-aligned manufacturing method of a Schottky gate FET. This method comprises the steps: forming a gate metallic layer on a semiconductor substrate and a mask overhanged on the metallic layer; ion-implanting impurity ions into the semiconductor substrate using the mask to form a source/drain region; depositing an insulator on the gate metallic layer side surface and the other surface below the mask; directionally etching said deposited insulator using the mask to expose the source/drain region; depositing a source/drain electrode using the mask; and removing the mask.
Claims27
A method of manufacturing a Schottky gate FET comprising the steps of:
- (a) forming a gate electrode of metallic material and a mask member on a semiconductor substrate, said gate electrode of metallic material being in Schottky contact to the semiconductor substrate, said mask member overhanging a periphery of the gate electrode;
- (b) ion-implanting impurities into the semiconductor substrate using said mask member as a mask, to form a source region and a drain region thereby forming an intermediate structure;
- (c) depositing insulator on a surface of the intermediate structure, including a side surface of the gate electrode overhung by the mask member;
- (d) etching said deposited insulator to expose the source region and the drain region using at least said mask member as a mask, while leaving the insulator at least at the side surface of the gate electrode;
- and
- (e) forming a source electrode and a drain electrode on the exposed source and drain regions.
A method of manufacturing a Schottky gate GaAs FET comprising the steps of:
- forming a Schottky gate electrode on a GaAs substrate and a mask member overhanging the gate electrode, the gate electrode being formed of a material selected from the group consisting of Ti, W, alloy of Ti and W, Ta, Hf, silicides and nitrides thereof, the overhanging mask including a silicon oxide layer;
- depositing an insulator layer on the exposed surfaces of the substrate, the gate electrode and the mask member, the insulator layer including a silicon nitride layer;
- directionally etching the insulator layer using said mask member as an etching mask to expose part of the GaAs substrate;
- and
- depositing current electrode on the exposed part of the GaAs substrate.
A method of manufacturing a Schottky gate FET, comprising the steps of:
- forming a shallow doped region in a surface of a semiconductor substrate;
- depositing a layer of Schottky material on the surface of the semiconductor substrate to form a Schottky contact therewith;
- forming an insulator layer on the surface of the layer of Schottky material;
- patterning the insulator layer to form a mask member;
- overly etching the layer of Schottky material using said mask member as an etching mask to form a Schottky gate electrode and to indent the side surface of the Schottky gate electrode below the mask member;
- depositing another insulator layer at least on the side surface of the Schottky gate electrode;
- directionally etching said another insulator layer using said mask member as an etching mask to expose the substrate surface;
- and
- depositing a metal layer on the exposed substrate surface.
Dependencies are inferred from the claim text.