US 4,546,475 A · Parity checking arrangement

Abstract

In a stored program controlled electronic telephone switching system transmission links are provided from a host office, provided with a central processor, to one or more remote offices, each provided with a remote processor. Data and control information are continually passed between the host office and each remote office in a digital time-division format. Data integrity is monitored through a cyclic odd and even patterned parity scheme which predetermines the parity of sequential time slots in one direction of transmission and reflects that parity pattern in the return direction of transmission between host office and remote offices. The patterned parity scheme detects hardware faults in the interface for the transmission links between host and remote offices on a continuous basis.

Claims15

Dependent claims

A transmission integrity arrangement for a two-way plural channel communication system comprising

means for interfacing with said channels,
first and second read-only memory (ROM) means for opposite transmission directions for storing a data word for each time slot in said system transmitted to and received from said interface means, said data word including a destination selection code for each channel, the sense of parity bits for the message traversing the channel, the parity of the subsequent ROM address value and the overall parity of the ROM data word;
counter means for controlling the read-out of the words of data from said first and second ROM means in sequence;
and
parity checking means for data received from said interface means and parity generator means for data transmitted to said interface means for producing localized indications of parity failure.

2 more elements

In a multiplexer for transferring a plurality of bidirectional signals between a plurality of parallel links, each including a plurality of time-divided channels, and a pair of bidirectional serial links having first and second preprogrammed memory means storing for opposite transmission directions a word of data for each channel in such system including a selection code and parity bits for parallel channel data, and the time-slot address and the parity of the overall data word;

counter means for controlling the read-out of words of data from such first and second memory means in sequence;
first and second parity control means for opposite transmission directions;
parity checking means and parity generating means for opposite transmission directions:
the method for maintaining continuous transmission integrity within said multiplexer comprising the steps of
(a) reading a word under the control of said counter means in sequence from said first memory to direct said first parity control means to apply a predetermined parity alternating from word to word to a signal word originating in a serial link destined for a particular parallel channel;
(b) repeating the parity of the last signal received in a particular parallel channel in the next signal originating in the particular parallel channel;
(c) comparing the parity of each signal proceeding from a particular parallel channel to a particular time slot serial link with a word stored in sequence in said second memory, and
(d) generating an error signal upon the failure of a comparison between a signal originating in a parallel channel and the time slot in the applicable link in said second memory.

5 more elements

Dependencies are inferred from the claim text.

Parity checking arrangement

Life of this patent

Parity checking arrangement

Life of this patent

Abstract

Claims15